PXAH40KFBE NXP Semiconductors, PXAH40KFBE Datasheet - Page 2

• Manufacturer Part Number: PXAH40KFBE
• Manufacturer: NXP Semiconductors

Specifications of PXAH40KFBE

• Cpu Family: XA
• Device Core: 80C51
• Device Core Size: 16b
• Frequency (max): 30MHz
• Interface Type: USART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• # I/os (max): 32
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.97V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
DESCRIPTION
The powerful 16-bit XA CPU core and rich feature set make the
XA-H3 and XA-H4 devices ideal for high-performance real-time
applications such as industrial control and networking. By supporting
of up to 32 MB of external memory, these devices provide a low-cost
solution to embedded applications of any complexity. Features like
DMA, memory controller and four advanced USARTs help solve I/O
intensive tasks with a minimum of CPU load.
FEATURES
ADDITIONAL XA-H4 FEATURES (NOT AVAILABLE ON XA-H3)
1999 Sep 24
Large Memory Support
De-multiplexed Address/Data Bus
Six Programmable Chip Selects
– Support for Unified Memory – allows easy user modification of
– External ISP Flash support for easy code download
Dynamic Bus Sizing – each of 6 Chip Selects can be programmed
for 8-bit or 16-bit bus.
Complete DRAM controller supports up to four banks of 8 MB each
Memory controller supports 16 MB in Unified Mode
Memory controller supports 32 MB in Harvard Mode
Serial ports are USARTs
– Synchronous capability up to 1 Mbps, and include
Single-chip 16-bit microcontroller
all code
HDLC/SDLC support
2
The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The
XA-H3/H4 devices are members of the Philips XA (eXtended
Architecture) family of high performance 16-bit microcontrollers.
The XA-H3 and XA-H4 are designed to significantly minimize the
need for external components.
Dynamic Bus Timing – each of 6 chip selects has individual
programmable bus timing.
32 Programmable General Purpose I/O Pins
Four USARTs with 230.4 kbps capability
Eight DMA Channels
– Four Match Characters are supported on each USART in
– Hardware Autobaud on all four USARTs in Async Mode
– USARTs are improved 85C30 style
Async Mode
Preliminary specification
XA-H4