PXAH40KFBE NXP Semiconductors, PXAH40KFBE Datasheet - Page 25

• Manufacturer Part Number: PXAH40KFBE
• Manufacturer: NXP Semiconductors

Specifications of PXAH40KFBE

• Cpu Family: XA
• Device Core: 80C51
• Device Core Size: 16b
• Frequency (max): 30MHz
• Interface Type: USART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• # I/os (max): 32
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.97V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
The XA-H4 has a standard XA CPU Interrupt Controller,
implemented with 15 Maskable Event Interrupts. Event Interrupts
are defined as maskable interrupts usually generated by hardware
events. However, in the XA-H4, 4 of the 15 Event Interrupts are
generated by software writing directly to the interrupt flag bit. These
4 interrupts are referred to as “High Priority Software Interrupts.”
1999 Sep 24
Single-chip 16-bit microcontroller
CD1_INT2
CTS0
CTS1
CTS2
CTS3
INT0
INT1
CD0
CD2
CD3
Software Ints
High Priority
HSWR 3–0
Interrupts
DMA
Autobaud
USART2/
USART0/
USART3
USART1
Timer 0
Timer 1
INT2
3–0
Figure 6. XA-H4 Interrupt Structure Overview
DMAH
DMAL
4
25
See the IC25 XA Data Handbook for a full explanation of the
exception structure, including event interrupts, of the XA CPU.
Because the High Priority Software Interrupts are not implemented
on all XA derivitives, they are explained in the XA-H4 User Manual .
Disable Bits
Interrupt
Enable/
Interrupt Controller
XA Core
Enable
Master
“EA”
Preliminary specification
XA-H4
Interrupt
To XA CPU
SU01276