PXAH40KFBE NXP Semiconductors, PXAH40KFBE Datasheet - Page 38

PXAH40KFBE

Manufacturer Part Number
PXAH40KFBE
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PXAH40KFBE

Cpu Family
XA
Device Core
80C51
Device Core Size
16b
Frequency (max)
30MHz
Interface Type
USART
Program Memory Type
ROMLess
Program Memory Size
Not Required
# I/os (max)
32
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.97V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / Rohs Status
Compliant

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Philips Semiconductors
1999 Sep 24
Single-chip 16-bit microcontroller
RAS (CS)
CASH, CASL
NOTE:
It is the minimum high time (thus RAS inactive) between two DRAM bus cycles on the same RAS pin.
ClkOut
CASL
RAS
D[7:0]
WE
A
RAS and CAS terminate together. The active low portion of RAS can be programmed to last from 3 to 6 clock cycles.
The high portion of RAS after Refresh can be programmed to last from 2 to 4 clock cycles. See Chapter 3 of the XA-H4 User Manual.
ClkOut
RAS
t
RP
minimum is specified for each of the 5 individual RAS pins (CS_RAS[5:1])
t
t
CHSL
CHAV
t
CHSL
t
RAS ADDRESS
AVSL
t
CLRL
Figure 20. DRAM 16-Bit Write on 8-Bit Bus (FPM or EDO DRAMs)
t
CHAV
t
CHSL
t
DVSL
t
t
CHAH
CHSL
t
Figure 22. RAS Precharge Time
AVSL
LS Byte
CAS ADDRESS EVEN
Figure 21. REFRESH
t
CHSH
38
t
CHAH
t
CHAV
t
RP
t
CHSH
t
CPWH
t
DVSL
CAS ADDRESS ODD
MS Byte
t
t
CHSH
CHAH
t
CHAV
Preliminary specification
SU01288
SU01287
SU01289
XA-H4

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