PXAH40KFBE NXP Semiconductors, PXAH40KFBE Datasheet - Page 17

• Manufacturer Part Number: PXAH40KFBE
• Manufacturer: NXP Semiconductors

Specifications of PXAH40KFBE

• Cpu Family: XA
• Device Core: 80C51
• Device Core Size: 16b
• Frequency (max): 30MHz
• Interface Type: USART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• # I/os (max): 32
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.97V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
1999 Sep 24
Data FIFO Register Ch.0 Tx
DMA Control Register Ch.1 Tx
FIFO Control & Status Register Ch.1 Tx
Segment Register Ch.1 Tx
Buffer Base Register Ch.1 Tx
Buffer Bound Register Ch.1 Tx
Address Pointer Reg Ch.1 Tx
Byte Count Register Ch.1 Tx
Data FIFO Register Ch.1 Lo Tx
Data FIFO Register Ch.1 Hi Tx
DMA Control Register Ch.2 Tx
FIFO Control & Status Register Ch.2 Tx
Segment Register Ch.2 Tx
Buffer Base Register Ch.2 Tx
Buffer Bound Register Ch.2 Tx
Address Pointer Reg Ch.2 Tx
Byte Count Register Ch.2 Tx
Data FIFO Register Ch.2 Lo Tx
Data FIFO Register Ch.2 Hi Tx
DMA Control Register Ch.3 Tx
FIFO Control & Status Register Ch.3 Tx
Segment Register Ch. 3 Tx
Buffer Base Register Ch. 3 Tx
Buffer Bound Register Ch.3 Tx
Address Pointer Reg Ch.3 Tx
Byte Count Register Ch.3 Tx
Data FIFO Register Ch.3 Lo Tx
Data FIFO Register Ch.3 Hi Tx
Rx Character Time Out Register Ch.0
Rx Character Time Out Register Ch.1
Rx Character Time Out Register Ch.2
Rx Character Time Out Register Ch.3
Global DMA Interrupt Register
GPOut
BDAEE (H4 Only)
BDCS (H4 Only)
Single-chip 16-bit microcontroller
MMR Name
or Read Only
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Miscellaneous DMA Registers
Autobaud Registers (H4 Only)
Size
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
180-1FEh
Address
Offset
14Eh
15Ah
15Ch
15Eh
16Ah
16Ch
16Eh
17Ah
17Ch
17Eh
150h
151h
152h
154h
156h
158h
160h
161h
162h
164h
166h
168h
170h
171h
172h
174h
176h
178h
200h
202h
204h
206h
210h
260h
270h
272h
17
14E = Byte2 = older
14F = Byte3 = younger
Control Register
Control & Status Register
Points to 64 k data segment
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Byte0 & 1
Byte2 & 3
Control Register
Control & Status Register
Points to 64 k data segment
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Byte0 & 1
Byte2 & 3
Control Register
Control & Status Register
Points to 64 k data segment
Wrap Reload Value for A15 – A8,
A7 – A0 reloaded to zero by hardware
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
Byte0 & 1
Byte2 & 3
RESERVED for future DMA
0 value disables counter interrupt
Same as above, for Rx1
Same as above, for Rx2
Same as above, for Rx3
DMA Interrupt Flags
GPOut[7] drives pin 98 (GPOut) through an inverter.
GPOut[6-0] are unused, and must be written with
zeroes.
Autobaud echo enable (H4 Only)
Autobaud Control and Status (H4 Only)
Description
Preliminary specification
XA-H4
Reset
0000h
00h
00h
00h
00h
0000h
0000h
0000h
0000h
0000h
00h
00h
00h
00h
0000h
0000h
0000h
0000h
0000h
00h
00h
00h
00h
0000h
0000h
0000h
0000h
0000h
–
00h
00h
00h
00h
0000h
8xh
00h
00h
Value