PXAH40KFBE NXP Semiconductors, PXAH40KFBE Datasheet - Page 16

PXAH40KFBE

Manufacturer Part Number
PXAH40KFBE
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PXAH40KFBE

Cpu Family
XA
Device Core
80C51
Device Core Size
16b
Frequency (max)
30MHz
Interface Type
USART
Program Memory Type
ROMLess
Program Memory Size
Not Required
# I/os (max)
32
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.97V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / Rohs Status
Compliant

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Philips Semiconductors
1999 Sep 24
Buffer Base Register Ch. 1 Rx
Buffer Bound Register Ch.1 Rx
Address Pointer Reg Ch.1 Rx
Byte Count Register Ch.1 Rx
Data FIFO Register Ch.1 Lo Rx
Data FIFO Register Ch.1 Hi Rx
DMA Control Register Ch.2 Rx
FIFO Control & Status Register Ch.2 Rx
Segment Register Ch. 2 Rx
Buffer Base Register Ch. 2 Rx
Buffer Bound Register Ch.2 Rx
Address Pointer Reg Ch.2 Rx
Byte Count Register Ch.2 Rx
Data FIFO Register Ch.2 Lo Rx
Data FIFO Register Ch.2 Hi Rx
DMA Control Register Ch.3 Rx
FIFO Control & Status Register Ch.3 Rx
Segment Register Ch. 3 Rx
Buffer Base Register Ch. 3 Rx
Buffer Bound Register Ch.3 Rx
Address Pointer Reg Ch.3 Rx
Byte Count Register Ch.3 Rx
Data FIFO Register Ch.3 Lo Rx
Data FIFO Register Ch.3 Hi Rx
DMA Control Register Ch.0 Tx
FIFO Control & Status Register Ch.0 Tx
Segment Register Ch. 0 Tx
Buffer Base Register Ch. 0 Tx
Buffer Bound Register Ch.0 Tx
Address Pointer Reg Ch.0 Tx
Byte Count Register Ch.0 Tx
Data FIFO Register Ch.0 Tx
Single-chip 16-bit microcontroller
MMR Name
or Read Only
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Size
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Tx DMA Registers
8
8
8
8
8
8
8
8
8
8
8
8
8
Address
Offset
12Ah
12Ch
12Eh
13Ah
13Ch
13Eh
14Ah
14Ch
11Ah
11Ch
11Eh
120h
121h
122h
124h
126h
128h
130h
131h
132h
134h
136h
138h
140h
141h
142h
144h
146h
148h
114h
116h
118h
16
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
11Ch = Byte 0 = older,
11Dh = Byte 1 = younger
11Eh = Byte 2 = older,
11Fh = Byte 3 = younger
Control Register
Control & Status Register
Points to 64 k data segment
Wrap Reload Value for A15 – A8, A7 – A0 reloaded to
zero by hardware
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
12Ch = Byte 0 = older,
12Dh = Byte 1 = younger
12Eh = Byte 2 = older,
12Fh = Byte 3 = younger
Control Register
Control & Status Register
Points to 64 k data segment
Wrap Reload Value for A15 – A8, A7 – A0 reloaded to
zero by hardware
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
13Ch = Byte 0 = older,
13Dh = Byte 1 = younger
13Eh = Byte 2 = older,
13Fh = Byte 3 = younger
Control Register
Control & Status Register
Points to 64 k data segment
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
Upper Bound (plus 1) on A15 – A0
Current Address pointer A15 – A0
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
14C = Byte0 = older
14D = Byte 1 = younger
Description
Preliminary specification
XA-H4
Reset
00h
0000h
0000h
0000h
00h
00h
00h
00h
00h
00h
00h
00h
0000h
0000h
0000h
00h
00h
00h
00h
00h
00h
00h
00h
0000h
0000h
0000h
00h
00h
00h
00h
00h
00h
00h
00h
0000h
0000h
0000h
0000h
Value

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