UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 592

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

590
2nd
Edition
Addition of 8.5 Program List
Modification of 8.6 (3) Capture register data retention timing
Addition of (11) STOP mode or main system clock stop mode setting
Modification of Figure 9-1 Block Diagram of 8-Bit Timer/Event Counter 50 and
Figure 9-2 Block Diagram of 8-Bit Timer/Event Counter 51
Deletion of Caution in Figure 9-5 Format of 8-Bit Timer Mode Control Register
50 (TMC50) and Figure 9-6 Format of 8-Bit Timer Mode Control Register 51
(TMC51)
Addition of [Setting] in 9.4.2 External event counter operation
Addition of description about frequency to [Setting] in 9.4.3 Square-wave output
(8-bit resolution) operation
Addition of descriptions about frequency and duty ratio to [Setting] in 9.4.4 8-bit
PWM output operation
Addition of 9.5 Program List
Deletion of 9.6 (2) Operation after compare register transition during timer
count operation in the previous edition
Deletion of oscillation stabilization time select register (OSTS) from 11.4
Registers to Control Watchdog Timer in the previous edition
Modification of Figure 12-1 Block Diagram of Clock Output/Buzzer Output
Controller
Addition of Figure 13-2 Format of A/D Conversion Result Register 0 (ADCR0)
Modification of description in 13.2 (3) Sample & hold circuit and (4) Voltage
comparator, and addition of (9) ADTRG pin
Addition of Table 13-2 ADCS0 and ADCE0 Settings and Figure 13-4 Timing
Chart When Boost Reference Voltage Generator Is Used
Addition of Table 13-3 Sampling Time and A/D Conversion Start Delay Time
of A/D Converter
Deletion of 13.6 (4) Noise countermeasures (those deleted are added to Figure
13-20 Example of Connecting Capacitor to AV
Example of Connection When Signal Source Impedance Is High)
Addition of (13) Input impedance of ANI0 to ANI7 pins
Modification of Figure 14-1 Block Diagram of Serial Interface UART0
Shift of description about asynchronous serial interface status register 0 (ASIS0)
from 14.3 Registers to Control Serial Interface UART0 to 14.2 Configuration
of Serial Interface UART0
Addition of Caution in Figure 14-7 Error Tolerance (When k = 0), Including
Sampling Errors
Modification of Caution in Figure 14-10 Timing of Asynchronous Serial
Interface Receive Completion Interrupt Request
Addition of (1) Registers to be used and (3) Relationship between main
system clock and baud rate in 14.4.3 Infrared data transfer mode
Addition of Table 14-6 Register Settings
APPENDIX E REVISION HISTORY
User’s Manual U14260EJ4V0UD
Contents
REF
Pin and Figure 13-22
CHAPTER 8 16-BIT
TIMER/EVENT
COUNTERS 00, 01
CHAPTER 9 8-BIT TIMER/
EVENT COUNTERS 50, 51
CHAPTER 11
WATCHDOG TIMER
CHAPTER 12 CLOCK
OUTPUT/BUZZER
OUTPUT CONTROLLER
CHAPTER 13 A/D
CONVERTER
CHAPTER 14 SERIAL
INTERFACE UART0
Applied to:
(2/7)