UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 430

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

21.1.2 Standby function control register
time select register (OSTS).
f
428
X
until release.
The wait time after the STOP mode is released upon an interrupt request is controlled by the oscillation stabilization
OSTS is set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. Therefore, when the STOP mode is released by inputting RESET, it takes 2
Remark For the registers that start, stop, or select the clock, see CHAPTER 7 CLOCK GENERATOR.
Note Expanded-specification products of PD780078 Subseries only.
Remark f
Caution The wait time after the STOP mode is released does not include the time (see “a” in the illustration
Address: FFFAH After reset: 04H R/W
Symbol
OSTS
below) from STOP mode release to clock oscillation start. This applies regardless of whether
STOP mode is released by RESET input or by interrupt request generation.
X
: Main system clock oscillation frequency
Figure 21-1. Format of Oscillation Stabilization Time Select Register (OSTS)
Other than above
OSTS2
7
0
0
0
0
0
1
OSTS1
6
0
0
0
1
1
0
X1 pin voltage
waveform
CHAPTER 21 STANDBY FUNCTION
OSTS0
5
0
0
1
0
1
0
User’s Manual U14260EJ4V0UD
STOP mode release
2
2
2
2
2
Setting prohibited
12
14
15
16
17
/f
/f
/f
/f
/f
4
0
X
X
X
X
X
a
Selection of Oscillation Stabilization Time
3
0
488 s
1.95 ms
3.91 ms
7.82 ms
15.6 ms
f
OSTS2
X
= 8.38 MHz
2
OSTS1
1
341 s
1.36 ms
2.73 ms
5.46 ms
10.9 ms
f
X
= 12 MHz
OSTS0
0
Note
17
/