UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 461

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8-bit
operation
Instruction
Group
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access is executed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Mnemonic
OR
XOR
CMP
2. The number of clocks applies when there is a program in the internal ROM.
3. n is the number of waits when external memory expansion area is read from.
register (PCC).
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
Note 3
Note 3
Note 3
CHAPTER 24 INSTRUCTION SET
User’s Manual U14260EJ4V0UD
Bytes
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
Note 2
9 + n
5 + n
9 + n
9 + n
9 + n
9 + n
5 + n
9 + n
9 + n
9 + n
9 + n
5 + n
9 + n
9 + n
9 + n
–
8
–
–
5
–
8
–
–
5
–
8
–
–
5
A
(saddr)
A
r
A
A
A
A
A
A
A
(saddr)
A
r
A
A
A
A
A
A
A – byte
(saddr) – byte
A – r
r – A
A – (saddr)
A – (addr16)
A – (HL)
A – (HL + byte)
A – (HL + B)
A – (HL + C)
r A
r
A byte
A r
A (saddr)
A (addr16)
A (HL)
A (HL + byte)
A (HL + B)
A (HL + C)
A
A
A
A
A
A
A
A
A
CPU
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
(HL + B)
(HL + C)
(saddr) byte
(saddr)
) selected by the processor clock control
Operation
byte
Z AC CY
Flag
459