UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 282

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(7) Port mode register 3 (PM3)
280
Address: FF23H After reset: FFH
Notes 5. Enabling or disabling the occurrence of the receive completion interrupt (INTSR2) in the case of an
Remark When receiving data in the multi-processor transfer mode, the receive completion interrupt (INTSR2)
PM3 is a register that sets the input/output of port 3 in 1-bit units.
To use the P34/TxD2/SI3 pin as a serial data output, set PM34 and the output latch of P34 to 0.
To use the P35/RxD2/SO3 pin as a serial data input, and the P36/ASCK2/SCK3 pin as a clock input, set PM35
and PM36 to 1. At this time, the output latches of P35 and P36 can be either 0 or 1.
PM3 is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Symbol
PM3
6. Even if MPIEN is cleared to 0, reception is started when the start bit is detected, in order to detect
7. When bit 7 (POWER2) and bit 5 (RXE2) of ASIM2 have not been set to 1, MPIEN2 cannot be cleared
8. Before setting ISMD2, clear bit 6 (TXE2) of asynchronous serial interface mode register 2 (ASIM2)
occurs, regardless of the value of MPIEN2, if data with the multi-processor appended bit set to “1” is
received. Usually, this receive data is an address (ID) that indicates the other party of communication.
The subsequent receive data can be ignored and the occurrence of an unnecessary receive completion
interrupt (INTSR2) can be disabled by comparing this received ID with the ID of the microcontroller
(for which software processing is necessary) and clearing MPIEN2 if the two IDs do not match.
error is affected by the setting of bit 0 (ISEM2) of ASIM2.
address (ID) reception. At this time, an error in the receive data is not detected if the multi-processor
appended bit is “0”. If data “1” is received by mistake, due to bit slip or other cause, when the multi-
processor appended bit is detected, however, ID reception is detected. Consequently, the error in
the receive data is identified, and the error interrupt signal may be generated and the error flag set.
to 0 (remain 1) even if 0 is written to it.
to 0.
PM3n
7
1
0
1
Output mode (output buffer on)
Input mode (output buffer off)
Figure 15-9. Format of Port Mode Register 3 (PM3)
PM36
6
CHAPTER 15 SERIAL INTERFACE UART2
R/W
PM35
5
User’s Manual U14260EJ4V0UD
I/O mode selection of P3n pin (n = 0 to 6)
PM34
4
PM33
3
PM32
2
PM31
1
PM30
0