UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 139

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UPD78F0078GK-9ET-A

Manufacturer Part Number
UPD78F0078GK-9ET-A
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0078GK-9ET-A

Lead Free Status / Rohs Status
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7.4.3 When subsystem clock is not used
connect the XT1 and XT2 pins as follows.
when the main system clock stops. To minimize leakage current, the above internal feedback resistor can be removed
by setting bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2 pins
as described above.
If it is not necessary to use the subsystem clock for low power consumption operations and watch operations,
XT1: Connect directly to V
XT2: Leave open
In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator
Remark The feedback resistor is required to control the bias point of the oscillation waveform so that the bias
point is in the middle of the power supply voltage.
DD0
Figure 7-7. Subsystem Clock Feedback Resistor
or V
DD1
Feedback resistor
CHAPTER 7 CLOCK GENERATOR
XT1
User’s Manual U14260EJ4V0UD
P-ch
FRC
XT2
137

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