UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 350

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

18.4 I
18.4.1 Pin configuration
up resistor is required.
348
The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows.
(1) SCL0 ········· This pin is used for serial clock input and output.
(2) SDA0 ········· This pin is used for serial data input and output.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-
2
C Bus Mode Functions
(Clock input)
Clock output
Data output
Data input
Master device
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
V
V
SS0
SS0
Figure 18-9. Pin Configuration Diagram
SCL0
SDA0
User’s Manual U14260EJ4V0UD
V
V
DD0
DD0
SDA0
SCL0
Slave device
V
V
SS0
SS0
(Clock output)
Clock input
Data output
Data input