ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 63

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
9397 750 14224
Product data sheet
Table 85:
Address: Value read from func0 or func1 of address 10h + 54h
Bit
17
16
15 to 10
9
8
7 to 5
Symbol
PESC
CSC
reserved
LSDA
PPS
reserved
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit
description
Description
Port Enable Status Change: This bit is set when hardware events cause
the PES (Port Enable Status) bit to be cleared. Changes from the HCD
writes do not set this bit. The HCD can write logic 1 to clear this bit. Writing
logic 0 has no effect.
0 — No change in PES
1 — Change in PES.
Connect Status Change: This bit is set whenever a connect or disconnect
event occurs. The HCD can write logic 1 to clear this bit. Writing logic 0 has
no effect. If CCS (Current Connect Status) is cleared when a Set Port
Reset, Set Port Enable or Set Port Suspend write occurs, this bit is set to
force the driver to re-evaluate the connection status because these writes
should not occur if the port is disconnected.
0 — No change in CCS
1 — Change in CCS.
Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a
Root Hub reset to inform the system that the device is attached.
-
On read, Low-Speed Device Attached: This bit indicates the speed of the
device attached to this port. When set, a low-speed device is attached to
this port. When cleared, a full-speed device is attached to this port. This bit
is valid only when CCS is set.
0 — Port is not suspended
1 — Port is suspended.
On write, Clear Port Power: The HCD can clear the PPS (Port Power
Status) bit by writing logic 1 to this bit. Writing logic 0 has no effect.
On read, Port Power Status: This bit reflects the port power status,
regardless of the type of power switching implemented. This bit is cleared if
an overcurrent condition is detected. The HCD can set this bit by writing Set
Port Power or Set Global Power. The HCD can clear this bit by writing Clear
Port Power or Clear Global Power. Power Switching Mode and
PortPowerControlMask[NDP] determine which power control switches are
enabled. In global switching mode (Power Switching Mode = 0), only
Set/Clear Global Power controls this bit. In the per-port power switching
(Power Switching Mode = 1), if the PortPowerControlMask[NDP] bit for the
port is set, only Set/Clear Port Power commands are enabled. If the mask is
not set, only Set/Clear Global Power commands are enabled.
When port power is disabled, bits CCS (Current Connect Status), PES (Port
Enable Status), PSS (Port Suspend Status) and PRS (Port Reset Status)
should be reset.
0 — Port power is off
1 — Port power is on.
On write, Set Port Power: The HCD can write logic 1 to set the PPS bit.
Writing logic 0 has no effect.
Remark: This bit always reads logic 1 if power switching is not supported.
-
…continued
Rev. 01 — 14 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
ISP1563
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