ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 103

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
Table 54: HcHCCA - Host Controller Communication
Table 55: HcHCCA - Host Controller Communication
Table 56: HcPeriodCurrentED - Host Controller
Table 57: HcPeriodCurrentED - Host Controller
Table 58: HcControlHeadED - Host Controller Control
Table 59: HcControlHeadED - Host Controller Control
Table 60: HcControlCurrentED - Host Controller
Table 61: HcControlCurrentED - Host Controller
Table 62: HcBulkHeadED - Host Controller Bulk Head
Table 63: HcBulkHeadED - Host Controller Bulk Head
Table 64: HcBulkCurrentED - Host Controller Bulk
Table 65: HcBulkCurrentED - Host Controller Bulk
Table 66: HcDoneHead - Host Controller Done Head
Table 67: HcDoneHead - Host Controller Done Head
Table 68: HcFmInterval - Host Controller Frame
Table 69: HcFmInterval - Host Controller Frame
Table 70: HcFmRemaining - Host Controller Frame
Table 71: HcFmRemaining - Host Controller Frame
Table 72: HcFmNumber - Host Controller Frame
Table 73: HcFmNumber - Host Controller Frame
Table 74: HcPeriodicStart - Host Controller Periodic
9397 750 14224
Product data sheet
Interrupt Disable register bit description . . . . .47
Area register bit allocation . . . . . . . . . . . . . . . .48
Area register bit description . . . . . . . . . . . . . . .48
Period Current Endpoint Descriptor
register bit allocation . . . . . . . . . . . . . . . . . . . .48
Period Current Endpoint Descriptor
register bit description . . . . . . . . . . . . . . . . . . .49
Head Endpoint Descriptor register bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Head Endpoint Descriptor register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .50
Control Current Endpoint Descriptor register
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Control Current Endpoint Descriptor register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .50
Endpoint Descriptor register bit allocation . . . .51
Endpoint Descriptor register bit description . . .51
Current Endpoint Descriptor register
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Current Endpoint Descriptor register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
register bit allocation . . . . . . . . . . . . . . . . . . . .52
register bit description . . . . . . . . . . . . . . . . . . .53
Interval register bit allocation . . . . . . . . . . . . . .53
Interval register bit description . . . . . . . . . . . . .54
Remaining register bit allocation . . . . . . . . . . .54
Remaining register bit description . . . . . . . . . .55
Number register bit allocation . . . . . . . . . . . . .55
Number register bit description . . . . . . . . . . . .56
Start register bit allocation . . . . . . . . . . . . . . . .56
Rev. 01 — 14 July 2005
Table 75: HcPeriodicStart - Host Controller Periodic
Table 76: HcLSThreshold - Host Controller LS
Table 77: HcLSThreshold - Host Controller LS
Table 78: HcRhDescriptorA - Host Controller Root
Table 79: HcRhDescriptorA - Host Controller Root
Table 80: HcRhDescriptorB - Host Controller Root
Table 81: HcRhDescriptorB - Host Controller Root
Table 82: HcRhStatus - Host Controller Root Hub
Table 83: HcRhStatus - Host Controller Root Hub
Table 84: HcRhPortStatus[4:1] - Host Controller Root
Table 85: HcRhPortStatus[4:1] - Host Controller Root
Table 86: Legacy support registers . . . . . . . . . . . . . . . . . 66
Table 87: Emulated registers . . . . . . . . . . . . . . . . . . . . . 66
Table 88: HceControl - Host Controller Emulation
Table 89: HceControl - Host Controller Emulation
Table 90: HceInput - Host Controller Emulation Input
Table 91: HceInput - Host Controller Emulation Input
Table 92: HceOutput - Host Controller Emulation
Table 93: HceOutput - Host Controller Emulation
Table 94: HceStatus - Host Controller Emulation
Table 95: HceStatus - Host Controller Emulation
Table 96: CAPLENGTH/HCIVERSION - Capability
Table 97: CAPLENGTH/HCIVERSION - Capability
Table 98: HCSPARAMS - Host Controller Structural
Table 99: HCSPARAMS - Host Controller Structural
Table 100:HCCPARAMS - Host Controller Capability
Start register bit description . . . . . . . . . . . . . . 56
Threshold register bit allocation . . . . . . . . . . . 57
Threshold register bit description . . . . . . . . . . 57
Hub Descriptor A register bit allocation . . . . . . 57
Hub Descriptor A register bit description . . . . . 58
Hub Descriptor B register bit allocation . . . . . . 59
Hub Descriptor B register bit description . . . . . 60
Status register bit allocation . . . . . . . . . . . . . . 60
Status register bit description . . . . . . . . . . . . . 61
Hub Port Status[4:1] register bit allocation . . . 62
Hub Port Status[4:1] register bit description . . 62
Control register bit allocation . . . . . . . . . . . . . . 66
Control register bit description . . . . . . . . . . . . 67
register bit allocation . . . . . . . . . . . . . . . . . . . . 68
register bit description . . . . . . . . . . . . . . . . . . . 68
Output register bit allocation . . . . . . . . . . . . . . 68
Output register bit description . . . . . . . . . . . . . 69
Status register bit allocation . . . . . . . . . . . . . . 69
Status register bit description . . . . . . . . . . . . . 70
Registers Length/Host Controller Interface
Version Number register bit allocation . . . . . . . 70
Registers Length/Host Controller Interface
Version Number register bit description . . . . . 71
Parameters register bit allocation . . . . . . . . . . 71
Parameters register bit description . . . . . . . . . 72
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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