ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 21

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
Table 11:
[1]
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
X is 1h for OHCI1 and OHCI2; X is 2h for EHCI.
Class Code register (address 09h) bit allocation
8.2.1.6 Class Code register
8.2.1.7 CacheLine Size register
23
15
R
R
R
7
Class Code is a 24-bit read-only register used to identify the generic function of the
device, and in some cases, a specific register-level programming interface.
shows the bit allocation of the register.
The Class Code register is divided into three byte-size fields. The upper byte is a base
class code that broadly classifies the type of function the device performs. The middle
byte is a sub-class code that identifies more specifically the function of the device. The
lower byte identifies a specific register-level programming interface, if any, so that
device-independent software can interact with the device.
Table 12:
The CacheLine Size register is a read and write single-byte register that specifies the
system CacheLine size in units of DWords. This register must be implemented by master
devices that can generate the Memory Write and Invalidate command. The value in this
register is also used by master devices to determine whether to use Read, Read Line or
Read Multiple commands to access the memory.
Slave devices that want to allow memory bursting using a CacheLine-wrap addressing
mode must implement this register to know when a burst sequence wraps to the
beginning of the CacheLine.
Bit
23 to 16
15 to 8
7 to 0
22
14
R
R
R
6
Class Code register (address 09h) bit description
Symbol
BCC[7:0]
SCC[7:0]
RLPI[7:0]
21
13
R
R
R
5
Rev. 01 — 14 July 2005
Description
Base Class Code: 0Ch is the base class code assigned to this byte. It
implies a serial bus controller.
Sub-Class Code: 03h is the sub-class code assigned to this byte. It
implies the USB Host Controller.
Register-Level Programming Interface: 10h is the programming
interface code assigned to OHCI, which is USB 1.1 specification
compliant. 20h is the programming interface code assigned to EHCI,
which is USB 2.0 specification compliant.
20
12
R
R
R
4
RLPI[7:0]
BCC[7:0]
SCC[7:0]
X0h
0Ch
03h
[1]
19
11
R
R
R
3
18
10
R
R
R
2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
17
R
R
R
9
1
ISP1563
Table 11
21 of 107
16
R
R
R
8
0