ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 25

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
9397 750 14224
Product data sheet
8.2.1.17 TRDY Timeout register
8.2.1.18 Retry Timeout register
8.2.2.1 SBRN register
8.2.2 Enhanced Host Controller-specific PCI registers
Table 24:
Legend: * reset value
[1]
This is a read and write register at address 40h. The default and recommended value is
00h; TRDY Timeout disabled. This value can, however, be modified. It is an
implementation-specific register, and not a standard PCI configuration register.
The TRDY timer is 13 bits. The lower 5 bits are fixed as logic 0 and the upper 8 bits are
determined by the TRDY Timeout register value. The time-out is calculated by multiplying
the 13-bit timer with the PCI CLK cycle time.
This register determines the maximum TRDY delay without asserting the UE
(Unrecoverable Error) bit. If TRDY is longer than the delay determined by this register
value, then the UE bit will be set.
The default value of this read and write register is 80h, and is located at address 41h. This
value can, however, be modified. Programming this register as 00h means that retry
time-out is disabled. This is an implementation-specific register, and not a standard PCI
configuration register.
The time-out is determined by multiplying the register value with the PCI CLK cycle time.
This register determines the maximum number of PCI retires before the UE bit is set. If the
number of retries is longer than the delay determined by this register value, then the UE
bit will be set.
In addition to the PCI configuration header registers, EHCI needs some additional PCI
configuration space registers to indicate the serial bus release number, downstream port
wake-up event capability, and adjust the USB bus frame length for Start-of-Frame (SOF).
The EHCI-specific PCI registers are given in
Table 25:
The Serial Bus Release Number (SBRN) register is a 1 B register, and the bit description
is given in
with which this USB Host Controller module is compliant.
Bit
7 to 0 MAX_LAT[7:0]
Offset
60h
61h
62h to 63h
The Max_Lat register bit description is given in
XX is 2Ah for OHCI1 and OHCI2; XX is 10h for EHCI.
Symbol
Table
Max_Lat - Maximum Latency register (address 3Fh) bit description
EHCI-specific PCI registers
26. This register contains the release number of the USB specification
Access Value
R
Rev. 01 — 14 July 2005
Register
Serial Bus Release Number (SBRN)
Frame Length Adjustment (FLADJ)
Port Wake Capability (PORTWAKECAP)
XXh*
[1]
Description
Max_Lat: It is used to specify how often the device
needs to gain access to the PCI bus.
Table
Table
25.
24.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
ISP1563
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