ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 19

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
Table 8:
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Status register (address 06h) bit allocation
8.2.1.4 Status register
FBBC
DPE
15
R
R
0
7
0
Table 7:
The Status register is a 2 B read-only register used to record status information on PCI
bus-related events. For bit allocation, see
Table 9:
Bit
2
1
0
Bit
15
14
13
reserved
SSE
14
R
R
0
6
0
Symbol
DPE
SSE
RMA
Symbol
BM
MS
IOS
Command register (address 04h) bit description
Status register (address 06h) bit description
66MC
RMA
Description
Detected Parity Error: This bit must be set by the device whenever it detects
a parity error, even if the parity error handling is disabled.
Signaled System Error: This bit must be set whenever the device asserts
SERR#. Devices that never assert SERR# do not need to implement this bit.
Received Master Abort: This bit must be set by a master device whenever
its transaction, except for Special Cycle, is terminated with Master-Abort. All
master devices must implement this bit.
13
R
R
0
5
0
Description
Bus Master: Controls the ability of a device to act as a master on the PCI
bus.
0 — Disables the device from generating PCI accesses. State after
RST# is logic 0.
1 — Allows the device to behave as a bus master.
Memory Space: Controls the response of a device to Memory Space
accesses.
0 — Disables the device response. State after RST# is logic 0.
1 — Allows the device to respond to Memory Space accesses.
I/O Space: Controls the response of a device to I/O space accesses.
0 — Disables the device response. State after RST# is logic 0.
1 — Allows the device to respond to I/O space accesses.
Rev. 01 — 14 July 2005
RTA
CL
12
R
R
0
4
1
Table
STA
11
R
R
0
3
0
8.
10
…continued
R
R
0
2
0
DEVSELT[1:0]
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
reserved
R
R
9
1
1
0
ISP1563
MDPE
19 of 107
R
R
8
0
0
0