ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 24

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
9397 750 14224
Product data sheet
8.2.1.14 Interrupt Line register
8.2.1.15 Interrupt Pin register
8.2.1.16 Min_Gnt and Max_Lat registers
Table 20:
Legend: * reset value
This is a 1 B register used to communicate interrupt line routing information. This register
must be implemented by any device or device function that uses an interrupt pin. The
interrupt allocation is done by the BIOS. The Power On Self Test (POST) software needs
to write the routing information to this register because it initializes and configures the
system. The value in this register specifies which input of the system interrupt controller(s)
the interrupt pin of the device is connected. This value is used by device drivers and
operating systems to determine priority and vector information. Values in this register are
system architecture specific. The bit description of the register is given in
Table 21:
Legend: * reset value
This 1 B register is use to specify which interrupt pin the device or device function uses.
A value of 1h corresponds to INTA#, 2h corresponds to INTB#, 3h corresponds to INTC#,
and 4h corresponds to INTD#. Devices or functions that do not use interrupt pin must set
this register to logic 0. The bit description is given in
Table 22:
Legend: * reset value
The Minimum Grant (Min_Gnt) and Maximum Latency (Max_Lat) registers are used to
specify the desired settings of the device for latency timer values. For both registers, the
value specifies a period of time in units of 250 ns. Logic 0 indicates that the device has no
major requirements for setting latency timers. The Min_Gnt register bit description is given
in
Table 23:
Legend: * reset value
[1]
Bit
7 to 0 CP[7:0]
Bit
7 to 0 IL[7:0]
Bit
7 to 0 IP[7:0]
Bit
7 to 0 MIN_GNT
Table
X is 1h for OHCI1 and OHCI2; X is 2h for EHCI.
Symbol
Symbol
Symbol
Symbol
[7:0]
23.
CP - Capabilities Pointer register (address 34h) bit description
IL - Interrupt Line register (address 3Ch) bit description
IP - Interrupt Pin register (address 3Dh) bit description
Min_Gnt - Minimum Grant register (address 3Eh) bit description
Access
R
Access
R/W
Access
R
Access
R
Rev. 01 — 14 July 2005
Value
DCh*
Value
00h*
Value
01h*
Value
0Xh*
[1]
Description
Capabilities Pointer: EHCI efficiently manages power
using this register. This Power Management register is
allocated at offset DCh. Only one Host Controller is
needed to manage power in the ISP1563.
Description
Interrupt Line: Indicates which IRQ is used to report
interrupt from the ISP1563.
Description
Interrupt Pin: INTA# is the default interrupt pin used
by the ISP1563.
Description
Min_Gnt: It is used to specify how long a burst period
the device needs, assuming a clock rate of 33 MHz.
Table
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
22.
HS USB PCI Host Controller
ISP1563
Table
21.
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