ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 62

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
Table 84:
Address: Value read from func0 or func1 of address 10h + 54h
[1]
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit allocation
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 85:
Address: Value read from func0 or func1 of address 10h + 54h
Bit
31 to 21
20
19
18
reserved
reserved
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Symbol
reserved
PRSC
OCIC
PSSC
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit
description
[1]
[1]
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Description
-
Port Reset Status Change: This bit is set at the end of the 10 ms port
reset signal. The HCD can write logic 1 to clear this bit. Writing logic 0 has
no effect.
0 — Port reset is not complete
1 — Port reset is complete.
Port Overcurrent Indicator Change: This bit is valid only if overcurrent
conditions are reported on a per-port basis. This bit is set when the Root
Hub changes the POCI (Port Overcurrent Indicator) bit. The HCD can write
logic 1 to clear this bit. Writing logic 0 has no effect.
0 — No change in POCI
1 — POCI has changed.
Port Suspend Status Change: This bit is set when the resume sequence
is completed. This sequence includes the 20 ms resume pulse, LS EOP
and 3 ms re-synchronization delay. The HCD can write logic 1 to clear this
bit. Writing logic 0 has no effect. This bit is also cleared when Reset Status
Change is set.
0 — Resume is not completed
1 — Resume is completed.
reserved
Rev. 01 — 14 July 2005
[1]
PRSC
PRS
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
[1]
OCIC
POCI
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
PSSC
R/W
R/W
R/W
PSS
R/W
26
18
10
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
PESC
LSDA
R/W
R/W
R/W
PES
R/W
25
17
0
0
9
0
1
0
ISP1563
CSC
CCS
PPS
R/W
R/W
R/W
R/W
62 of 107
24
16
0
0
8
0
0
0