ADV7180BSTZ Analog Devices Inc, ADV7180BSTZ Datasheet - Page 9
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ADV7180BSTZ
Manufacturer Part Number
ADV7180BSTZ
Description
IC VIDEO DECODER SDTV 64-LQFP
Manufacturer
Analog Devices Inc
Type
Video Decoderr
Datasheet
1.ADV7180BSTZ.pdf
(116 pages)
Specifications of ADV7180BSTZ
Design Resources
Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
Applications
Digital Cameras, Mobile Phones, Portable Video
Voltage - Supply, Analog
1.71 V ~ 1.89 V
Voltage - Supply, Digital
1.65 V ~ 2 V
Mounting Type
Surface Mount
Package / Case
64-LQFP
Resolution (bits)
10bit
Input Format
Analog
Output Format
Digital
Adc Sample Rate
57.27MSPS
Power Dissipation Pd
15µW
No. Of Input Channels
6
Supply Voltage Range
1.71V To 1.89V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADV7180LQEBZ - BOARD EVALUATION ADV7180EVAL-ADV7180LFEBZ - BOARD EVAL FOR ADV7180 LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADV7180BSTZ
Manufacturer:
AMIS
Quantity:
6 240
Company:
Part Number:
ADV7180BSTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADV7180BSTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
ADV7180BSTZ-REEL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
TIMING SPECIFICATIONS
Guaranteed by characterization. A
at operating temperature range, unless otherwise noted.
Table 5.
Parameter
SYSTEM CLOCK AND CRYSTAL
I
RESET FEATURE
CLOCK OUTPUTS
DATA AND CONTROL OUTPUTS
Timing Diagrams
2
C PORT
Nominal Frequency
Frequency Stability
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Times
SCLK and SDA Fall Times
Setup Time for Stop Condition
Reset Pulse Width
LLC Mark Space Ratio
Data Output Transitional Time
Data Output Transitional Time
SDATA
SCLK
OUTPUTS P0 TO P15, VS,
VDD
= 1.71 V to 1.89 V, D
OUTPUT LLC
t
3
HS, FIELD,
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
11
12
2
:t
SFL
10
Figure 7. Pixel Port and Control Output Timing
t
6
Test Conditions
Negative clock edge to start of valid data
(t
End of valid data to negative clock edge
(t
ACCESS
HOLD
t
7
VDD
t
1
= t
Rev. F | Page 9 of 116
t
Figure 6. I
= t
5
= 1.65 V to 2.0 V, D
9
10
+ t
− t
12
t
)
9
11
2
C Timing
t
12
)
t
11
t
10
VDDIO
t
= 1.62 V to 3.6 V, P
3
t
4
Min
0.6
1.3
0.6
0.6
100
5
45:55
t
8
Typ
28.6363
0.6
VDD
= 1.65 V to 2.0 V, specified
Max
±50
400
300
300
55:45
3.6
2.4
ADV7180
Unit
MHz
ppm
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ms
% duty cycle
ns
ns