ADV7180BSTZ Analog Devices Inc, ADV7180BSTZ Datasheet - Page 80
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ADV7180BSTZ
Manufacturer Part Number
ADV7180BSTZ
Description
IC VIDEO DECODER SDTV 64-LQFP
Manufacturer
Analog Devices Inc
Type
Video Decoderr
Datasheet
1.ADV7180BSTZ.pdf
(116 pages)
Specifications of ADV7180BSTZ
Design Resources
Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
Applications
Digital Cameras, Mobile Phones, Portable Video
Voltage - Supply, Analog
1.71 V ~ 1.89 V
Voltage - Supply, Digital
1.65 V ~ 2 V
Mounting Type
Surface Mount
Package / Case
64-LQFP
Resolution (bits)
10bit
Input Format
Analog
Output Format
Digital
Adc Sample Rate
57.27MSPS
Power Dissipation Pd
15µW
No. Of Input Channels
6
Supply Voltage Range
1.71V To 1.89V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADV7180LQEBZ - BOARD EVALUATION ADV7180EVAL-ADV7180LFEBZ - BOARD EVAL FOR ADV7180 LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADV7180BSTZ
Manufacturer:
AMIS
Quantity:
6 240
Company:
Part Number:
ADV7180BSTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADV7180BSTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
ADV7180BSTZ-REEL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADV7180
Table 106. Interrupt System Register Map Details
Dec
64
66
67
68
69
70
71
72
73
74
75
76
78
79
80
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
Address
Hex
40
42
43
44
45
46
47
48
49
4A
4B
4C
4E
4F
50
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
Register Name
Interrupt
Configuration 1
Interrupt Status 1
Interrupt Clear 1
Interrupt Mask 1
Raw Status 1
Interrupt Status 2
Interrupt Clear 2
Interrupt Mask 2
Raw Status 2
Interrupt Status 3
Interrupt Clear 3
Interrupt Mask 3
Interrupt Status 4
Interrupt Clear 4
Interrupt Mask 4
VDP_Config_1
VDP_Config_2
VDP_ADF_Config_1 RW
VDP_ADF_Config_2 RW
VDP_LINE_00E
VDP_LINE_00F
VDP_LINE_010
VDP_LINE_011
VDP_LINE_012
VDP_LINE_013
VDP_LINE_014
VDP_LINE_015
VDP_LINE_016
VDP_LINE_017
VDP_LINE_018
VDP_LINE_019
VDP_LINE_01A
VDP_LINE_01B
VDP_LINE_01C
VDP_LINE_01D
VDP_LINE_01E
VDP_LINE_01F
RW
RW
R
W
RW
R
R
W
RW
R
R
W
RW
R
W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
7
INTRQ_DUR_
SEL[1]
MPU_STIM_
INTRQ
MPU_STIM_
INTRQ_Q
MPU_STIM_
INTRQ_CLR
MPU_STIM_
INTRQ_MSKB
ADF_ENABLE
DUPLICATE_ADF
MAN_LINE_PGM
VBI_DATA_
P6_N23[3]
VBI_DATA_
P7_N24[3]
VBI_DATA_
P8_N25[3]
VBI_DATA_
P9[3]
VBI_DATA_
P10[3]
VBI_DATA_
P11[3]
VBI_DATA_
P12_N10[3]
VBI_DATA_
P13_N11[3]
VBI_DATA_
P14_N12[3]
VBI_DATA_
P15_N13[3]
VBI_DATA_
P16_N14[3]
VBI_DATA_
P17_N15[3]
VBI_DATA_
P18_N16[3]
VBI_DATA_
P19_N17[3]
VBI_DATA_
P20_N18[3]
VBI_DATA_
P21_N19[3]
VBI_DATA_
P22_N20[3]
6
INTRQ_DUR_
SEL[0]
MV_PS_CS_Q
MV_PS_CS_CLR
MV_PS_CS_
MSKB
VDP_VITC_Q
VDP_VITC_CLR
VDP_VITC_MSKB
ADF_MODE[1]
VBI_DATA_
P6_N23[2]
VBI_DATA_
P7_N24[2]
VBI_DATA_
P8_N25[2]
VBI_DATA_
P9[2]
VBI_DATA_
P10[2]
VBI_DATA_
P11[2]
VBI_DATA_
P12_N10[2]
VBI_DATA_
P13_N11[2]
VBI_DATA_
P14_N12[2]
VBI_DATA_
P15_N13[2]
VBI_DATA_
P16_N14[2]
VBI_DATA_
P17_N15[2]
VBI_DATA_
P18_N16[2]
VBI_DATA_
P19_N17[2]
VBI_DATA_
P20_N18[2]
VBI_DATA_
P21_N19[2]
VBI_DATA_
P22_N20[2]
1, 2
5
MV_INTRQ_
SEL[1]
SD_FR_CHNG_Q
SD_FR_CHNG_
CLR
SD_FR_CHNG_
MSKB
PAL_SW_LK_
CHNG_Q
PAL_SW_LK_
CHNG_CLR
PAL_SW_LK_
CHNG_MSKB
ADF_MODE[0]
ADF_SDID[5]
VBI_DATA_
P6_N23[1]
VBI_DATA_
P7_N24[1]
VBI_DATA_
P8_N25[1]
VBI_DATA_
P9[1]
VBI_DATA_
P10[1]
VBI_DATA_
P11[1]
VBI_DATA_
P12_N10[1]
VBI_DATA_
P13_N11[1]
VBI_DATA_
P14_N12[1]
VBI_DATA_
P15_N13[1]
VBI_DATA_
P16_N14[1]
VBI_DATA_
P17_N15[1]
VBI_DATA_
P18_N16[1]
VBI_DATA_
P19_N17[1]
VBI_DATA_
P20_N18[1]
VBI_DATA_
P21_N19[1]
VBI_DATA_
P22_N20[1]
Rev. F | Page 80 of 116
4
MV_INTRQ_
SEL[0]
EVEN_FIELD
SD_FIELD_
CHNGD_Q
SD_FIELD_
CHNGD_CLR
SD_FIELD_
CHNGD_MSKB
SCM_LOCK
SCM_LOCK_
CHNG_Q
SCM_LOCK_
CHNG_CLR
SCM_LOCK_
CHNG_MSKB
VDP_GS_VPS_
PDC_UTC_
CHNG_Q
VDP_GS_VPS_
PDC_UTC_
CHNG_CLR
VDP_GS_VPS_
PDC_UTC_
CHNG_MSKB
AUTO_DETECT_
GS_TYPE
ADF_DID[4]
ADF_SDID[4]
VBI_DATA_
P6_N23[0]
VBI_DATA_
P7_N24[0]
VBI_DATA_
P8_N25[0]
VBI_DATA_
P9[0]
VBI_DATA_
P10[0]
VBI_DATA_
P11[0]
VBI_DATA_
P12_N10[0]
VBI_DATA_
P13_N11[0]
VBI_DATA_
P14_N12[0]
VBI_DATA_
P15_N13[0]
VBI_DATA_
P16_N14[0]
VBI_DATA_
P17_N15[0]
VBI_DATA_
P18_N16[0]
VBI_DATA_
P19_N17[0]
VBI_DATA_
P20_N18[0]
VBI_DATA_
P21_N19[0]
VBI_DATA_
P22_N20[0]
3
SD_AD_CHNG_Q SD_H_LOCK_
SD_AD_CHNG_
CLR
SD_AD_CHNG_
MSKB
WST_PKT_
DECODE_
DISABLE
ADF_DID[3]
ADF_SDID[3]
VBI_DATA_
P318[3]
VBI_DATA_
P319_N286[3]
VBI_DATA_
P320_N287[3]
VBI_DATA_
P321_N288[3]
VBI_DATA_
P322[3]
VBI_DATA_
P323[3]
VBI_DATA_
P324_N272[3]
VBI_DATA_
P325_N273[3]
VBI_DATA_
P326_N274[3]
VBI_DATA_
P327_N275[3]
VBI_DATA_
P328_N276[3]
VBI_DATA_
P329_N277[3]
VBI_DATA_
P330_N278[3]
VBI_DATA_
P331_N279[3]
VBI_DATA_
P332_N280[3]
VBI_DATA_
P333_N281[3]
VBI_DATA_
P334_N282[3]
VBI_DATA_
P335_N283[3]
2
MPU_STIM_
INTRQ
SD_H_LOCK
CHNG_Q
SD_H_LOCK_
CHNG_CLR
SD_H_LOCK_
CHNG_MSKB
VDP_CGMS_
WSS_CHNGD_Q
VDP_CGMS_
WSS_CHNGD_
CLR
VDP_CGMS_
WSS_CHNGD_
MSKB
VDP_TTXT_
TYPE_MAN_
ENABLE
ADF_DID[2]
ADF_SDID[2]
VBI_DATA_
P318[2]
VBI_DATA_
P319_N286[2]
VBI_DATA_
P320_N287[2]
VBI_DATA_
P321_N288[2]
VBI_DATA_
P322[2]
VBI_DATA_
P323[2]
VBI_DATA_
P324_N272[2]
VBI_DATA_
P325_N273[2]
VBI_DATA_
P326_N274[2]
VBI_DATA_
P327_N275[2]
VBI_DATA_
P328_N276[2]
VBI_DATA_
P329_N277[2]
VBI_DATA_
P330_N278[2]
VBI_DATA_
P331_N279[2]
VBI_DATA_
P332_N280[2]
VBI_DATA_
P333_N281[2]
VBI_DATA_
P334_N282[2]
VBI_DATA_
P335_N283[2]
INTRQ_OP_
SEL[1]
SD_UNLOCK_Q
SD_UNLOCK_
CLR
SD_UNLOCK_
MSKB
GEMD_Q
GEMD_CLR
GEMD_MSKB
SD_V_LOCK
SD_V_LOCK_
CHNG_Q
SD_V_LOCK_
CHNG_CLR
SD_V_LOCK_
CHNG_MSKB
VDP_TTXT_
TYPE_MAN[1]
ADF_DID[1]
ADF_SDID[1]
VBI_DATA_
P318[1]
VBI_DATA_
P319_N286[1]
VBI_DATA_
P320_N287[1]
VBI_DATA_
P321_N288[1]
VBI_DATA_
P322[1]
VBI_DATA_
P323[1]
VBI_DATA_
P324_N272[1]
VBI_DATA_
P325_N273[1]
VBI_DATA_
P326_N274[1]
VBI_DATA_
P327_N275[1]
VBI_DATA_
P328_N276[1]
VBI_DATA_
P329_N277[1]
VBI_DATA_
P330_N278[1]
VBI_DATA_
P331_N279[1]
VBI_DATA_
P332_N280[1]
VBI_DATA_
P333_N281[1]
VBI_DATA_
P334_N282[1]
VBI_DATA_
P335_N283[1]
1
0
INTRQ_OP_SEL[0] 0001x000
SD_LOCK_Q
SD_LOCK_CLR
SD_LOCK_MSKB x0000000
CCAPD
CCAPD_Q
CCAPD_CLR
CCAPD_MSKB
SD_OP_50Hz
SD_OP_CHNG_Q
SD_OP_CHNG_
CLR
SD_OP_CHNG_
MSKB
VDP_CCAPD_Q
VDP_CCAPD_CLR 00x0x0x0
VDP_CCAPD_
MSKB
VDP_TTXT_
TYPE_MAN[0]
ADF_DID[0]
ADF_SDID[0]
VBI_DATA_
P318[0]
VBI_DATA_
P319_N286[0]
VBI_DATA_
P320_N287[0]
VBI_DATA_
P321_N288[0]
VBI_DATA_
P322[0]
VBI_DATA_
P323[0]
VBI_DATA_
P324_N272[0]
VBI_DATA_
P325_N273[0]
VBI_DATA_
P326_N274[0]
VBI_DATA_
P327_N275[0]
VBI_DATA_
P328_N276[0]
VBI_DATA_
P329_N277[0]
VBI_DATA_
P330_N278[0]
VBI_DATA_
P331_N279[0]
VBI_DATA_
P332_N280[0]
VBI_DATA_
P333_N281[0]
VBI_DATA_
P334_N282[0]
VBI_DATA_
P335_N283[0]
x0000000
0xx00000
0xx00000
00x0x0x0
Reset Value (Hex)
xx000000
xx000000
10001000
0001xx00
00010101
0x101010
0xxx0000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
10
00
00
00
00
00
00
00
00
88
10
15
2A
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00