ADV7180BSTZ Analog Devices Inc, ADV7180BSTZ Datasheet - Page 77

• Manufacturer Part Number: ADV7180BSTZ
• Description: IC VIDEO DECODER SDTV 64-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180BSTZ

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Resolution (bits): 10bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 57.27MSPS
• Power Dissipation Pd: 15µW
• No. Of Input Channels: 6
• Supply Voltage Range: 1.71V To 1.89V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7180LQEBZ - BOARD EVALUATION ADV7180EVAL-ADV7180LFEBZ - BOARD EVAL FOR ADV7180 LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER ACCESS
The MPU can write to or read from all of the ADV7180 registers
except the subaddress register, which is write only. The subaddress
register determines which register the next read or write operation
accesses. All communications with the part through the bus start
with an access to the subaddress register. A read/write operation is
then performed from or to the target address, which increments
to the next address until a stop command on the bus is performed.
REGISTER PROGRAMMING
The following sections describe the configuration for each
register. The communication register is an 8-bit, write-only
register. After the part is accessed over the bus and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to or from which register the operation
takes place. Table 105 lists the various operations under the
control of the subaddress register for the control port.
SUB_USR_EN, Address 0x0E[5]
This bit splits the register map at Register 0x40.
NORMAL REGISTER SPACE
ADDRESS 0x0E BIT 5 = 0b
ADDRESS 0x40 ≥ 0xFF
ADDRESS 0x00 ≥ 0x3F
COMMON I
Figure 53. Register Access—User Map and User Sub Map
USER MAP
I
2
C SPACE
2
C SPACE
INTERRUPT AND VDP REGISTER SPACE
USER SUB MAP
ADDRESS 0x0E BIT 5 = 1b
ADDRESS 0x40 ≥ 0x9C
I
2
C SPACE
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Register Select (SR7 to SR0)
These bits are set up to point to the required starting address.
I
An I
and is therefore distributed over two or more I
example, HSB[10:0].
When such a parameter is changed using two or more I
operations, the parameter may hold an invalid value for the
time between the first I
being completed. In other words, the top bits of the parameter
may hold the new value while the remaining bits of the parameter
still hold the previous value.
To avoid this problem, the I
of the parameter in local memory, and all bits of the parameter
are updated together once the last register write operation has
completed.
The correct operation of the I
•
•
2
C SEQUENCER
2
All I
written to in order of ascending addresses. For example, for
HSB[10:0], write to Address 0x34 first, followed by 0x35,
and so on.
No other I
writes for the sequence. For example, for HSB[10:0], write to
Address 0x34 first, immediately followed by 0x35, and so on.
C sequencer is used when a parameter exceeds eight bits
2
C registers for the parameter in question must be
2
C can take place between the two (or more) I
2
C being completed and the last I
2
2
C sequencer holds the updated bits
C sequencer relies on the following:
2
C registers, for
ADV7180
2
C write
2
C
2
C