ADV7180BSTZ Analog Devices Inc, ADV7180BSTZ Datasheet - Page 59

• Manufacturer Part Number: ADV7180BSTZ
• Description: IC VIDEO DECODER SDTV 64-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180BSTZ

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Resolution (bits): 10bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 57.27MSPS
• Power Dissipation Pd: 15µW
• No. Of Input Channels: 6
• Supply Voltage Range: 1.71V To 1.89V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7180LQEBZ - BOARD EVALUATION ADV7180EVAL-ADV7180LFEBZ - BOARD EVAL FOR ADV7180 LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

I
Dedicated I
WSS, Gemstar, VPS, PDC/UTC, and VITC. Because teletext is a
high data rate standard, data extraction is supported only through
the ancillary data packet.
User Interface for I
The VDP decodes all enabled VBI data standards in real time.
Because the I
rate, when the registers are accessed, they may be updated with
data from the next line. To avoid this, VDP has a self-clearing
clear bit and an available (AVL) status bit accompanying all I
readback registers.
The user must clear the I
the clear bit. This resets the state of the available bit to low and
indicates that the data in the associated readback registers is not
valid. After the VDP decodes the next line of the corresponding
VBI data, the decoded data is placed into the I
register and the available bit is set to high to indicate that valid
data is now available.
Though the VDP decodes this VBI data in subsequent lines if
present, the decoded data is not updated to the readback registers
until the clear bit is set high again. However, this data is
available through the 656 ancillary data packets.
The clear and available bits are in the VDP_STATUS_CLEAR
(0x78, user sub map, write only) and VDP_STATUS (0x78, user
sub map, read only) registers, respectively.
Example I
The following tasks must be performed to read one packet
(line) of PDC data from the decoder:
1.
2.
3.
4.
To read a packet of CCAP, CGMS, or WSS data, Step 1 to Step 3
are required only because they have dedicated registers.
VDP—Content-Based Data Update
For certain standards, such as WSS, CGMS, Gemstar, PDC, UTC,
and VPS, the information content in the signal transmitted remains
the same over numerous lines, and the user may want to be notified
only when there is a change in the information content or loss of
the information content. The user must enable content-based
updating for the required standard through the GS_VPS_PDC_
UTC_CB_CHANGE and WSS_CGMS_CB_CHANGE bits.
Therefore, the available bit shows the availability of that
standard only when its content has changed.
2
C Interface
Write 10 to I
map) to specify that PDC data must be updated to I
registers.
Write high to the GS_PDC_VPS_UTC_CLEAR bit (0x78,
user sub map) to enable I
Poll the GS_PDC_VPS_UTC_AVL bit (0x78, user sub
map) going high to check the availability of the PDC
packets.
Read the data bytes from the PDC I
Step 1 to Step 3 to read another line or packet of data.
2
2
C readback registers are available for CCAP, CGMS,
C Readback Procedure
2
C access speed is much lower than the decoded
2
C_GS_VPS_PDC_UTC[1:0] (0x9C, user sub
2
C Readback Registers
2
C readback register by writing a high to
2
C register updating.
2
C registers. Repeat
2
C readback
2
C
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2
C
Content-based updating also applies to lines with lost data.
Therefore, for standards like VPS, Gemstar, CGMS, and WSS, if no
data arrives in the next four lines programmed, the corresponding
available bit in the VDP_STATUS register is set high and the
content in the I
must write high to the corresponding clear bit so that when a
valid line is decoded after some time, the decoded results are
available in the I
If content-based updating is enabled, the available bit is set high
(assuming the clear bit was written) in the following cases:
•
•
•
GS_VPS_PDC_UTC_CB_CHANGE, Enable Content-
Based Updating for Gemstar/VPS/PDC/UTC,
Address 0x9C[5], User Sub Map
Setting GS_VPS_PDC_UTC_CB_CHANGE to 0 disables
content-based updating.
Setting GS_VPS_PDC_UTC_CB_CHANGE to 1 (default)
enables content-based updating.
WSS_CGMS_CB_CHANGE, Enable Content-Based
Updating for WSS/CGMS, Address 0x9C[4],
User Sub Map
Setting WSS_CGMS_CB_CHANGE to 0 disables content-based
updating.
Setting WSS_CGMS_CB_CHANGE to 1 (default) enables
content-based updating.
VDP—Interrupt-Based Reading of VDP I
Some VDP status bits are also linked to the interrupt request
controller so that the user does not have to poll the available status
bit. The user can configure the video decoder to trigger an
interrupt request on the INTRQ pin in response to the valid
data available in the I
the following data types:
•
•
The data contents have changed.
Data was being decoded and four lines with no data have
been detected.
No data was being decoded and new data is now being
decoded.
CGMS or WSS. The user can select either triggering an
interrupt request each time sliced data is available or
triggering an interrupt request only when the sliced data
has changed. Selection is made via the WSS_CGMS_CB_
CHANGE bit.
Gemstar, PDC, VPS, or UTC. The user can select to trigger
an interrupt request each time sliced data is available or to
trigger an interrupt request only when the sliced data has
changed. Selection is made via the GS_VPS_PDC_UTC_
CB_CHANGE bit.
2
2
C registers for that standard is set to 0. The user
C registers, with the available status bit set high.
2
C registers. This function is available for
2
C Registers
ADV7180