MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 127

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

3.3
This section provides a detailed description of all registers.
integration module.
Freescale Semiconductor
0x001E - 0x001F
0x0006 - 0x0007
Address Offset
Memory Map and Register Definition
0x000C
0x000D
0x001C
0x001D
0x000A
0x000B
0x000E
0x000F
0x001A
0x001B
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0008
0x0009
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
0x0016
0x0017
0x0018
0x0019
Port T I/O Register (PTT)
Port T Input Register (PTIT)
Port T Data Direction Register (DDRT)
Port T Reduced Drive Register (RDRT)
Port T Pull Device Enable Register (PERT)
Port T Polarity Select Register (PPST)
Reserved
Port S I/O Register (PTS)
Port S Input Register (PTIS)
Port S Data Direction Register (DDRS)
Port S Reduced Drive Register (RDRS)
Port S Pull Device Enable Register (PERS)
Port S Polarity Select Register (PPSS)
Port S Wired-OR Mode Register (WOMS)
Reserved
Port M I/O Register (PTM)
Port M Input Register (PTIM)
Port M Data Direction Register (DDRM)
Port M Reduced Drive Register (RDRM)
Port M Pull Device Enable Register (PERM)
Port M Polarity Select Register (PPSM)
Port M Wired-OR Mode Register (WOMM)
Reserved
Port P I/O Register (PTP)
Port P Input Register (PTIP)
Port P Data Direction Register (DDRP)
Port P Reduced Drive Register (RDRP)
Port P Pull Device Enable Register (PERP)
Port P Polarity Select Register (PPSP)
Reserved
Table 3-2. PIM9HZ256 Memory Map
MC9S12E128 Data Sheet, Rev. 1.07
Use
Table 3-2
Chapter 3 Port Integration Module (PIM9E128V1)
is a standard memory map of port
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
R
R
R
R
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