TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 93

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

This resister set the clearing standby request active level of external interrupt INTC to INTF.
CGIMCGD
7.6.3.4
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
(Note1)
(Note2)
CG Interrupt Mode Control Register D
“0” is read Active state setting of INTC standby
“0” is read Active state setting of INTD standby
“0” is read Active state setting of INTE standby
“0” is read Active state setting of INTF standby
EMSTxx is effective only when EMCGxx is set to "100" for both rising and falling
edge. The active level used for the reset of standby can be checked by referring
EMSTxx. If interrupts are cleared with the CGICRCG register, EMSTxx is also
cleared.
Please specify the bit for the edge first and then specify the bit for the <INTxEN>.
Setting them simultaneously is prohibited.
15
23
31
7
R
R
R
R
0
0
0
0
clear request. (101 to 111: setting
prohibited)
clear request. (101 to 111: setting
prohibited)
clear request. (101 to 111: setting
prohibited)
clear request. (101 to 111: setting
prohibited)
EMCGC2 EMCGC1
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
EMCGD2 EMCGD1
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
EMCGE2 EMCGE1
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
EMCGF2
14
22
30
6
0
0
0
0
EMCGF1
TMPM370 7-55
R/W
R/W
R/W
R/W
13
21
29
5
1
1
1
1
EMCGC0
EMCGD0
EMCGE0
EMCGF0
12
20
28
4
0
0
0
0
standby clear request
standby clear request
standby clear request
standby clear request
Active state of INTC
Active state of INTD
Active state of INTE
Active state of INTF
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
EMSTC1
EMSTD1
EMSTE1
EMSTF1
11
19
27
3
0
0
0
0
EMSTC0
EMSTD0
EMSTE0
EMSTF0
10
18
26
R
R
R
R
2
0
0
0
0
Reads as
undefined.
Reads as
undefined.
Reads as
undefined.
Reads as
undefined.
Undefined
Undefined
Undefined
Undefined
17
25
1
9
INTC clear
input
0: Disable
1: Enable
INTD clear
input
0: Disable
1: Enable
INTE clear
input
0: Disable
1: Enable
INTF clear
input
0: Disable
1: Enable
INTCEN
INTEEN
INTDEN
TMPM370
INTFEN
Interrupt
R/W
R/W
R/W
R/W
16
24
0
8
0
0
0
0