TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet
TMPM370FYDFG
Specifications of TMPM370FYDFG
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TMPM370FYDFG Summary of contents
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... RISC Microcontroller TX03 Series TMPM370FYDFG/FYFG Semiconductor Company ...
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Date 2010/10/18 2011/3/7 Revision History Revision Rev 1 Rev 2 Contents Revised First Release ...
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ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. **************************************************************************************************************** TMPM370 1-1 ...
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... RISC microcontroller TX03 series TMPM370FYDFG TX03 series is a 32-bit RISC microcontroller with an ARM Product No. On chip Flash ROM TMPM370FYDFG TMPM370FYFG 1.1 Features ( 1 ) ARM Cortex-M3 microcontroller core 1) Improved code efficiency has been realized through the use of Thumb - New 16-bit Thumb - New 32-bit Thumb instructions for improved performance and code size. ...
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Vector engine(VE): 1 unit - Calculationg circuit for motor control - corresponding to 2 motors ( 9 ) Programmable motor driver(PMD): 2channel - 3phase complementary PWM generator - Synchronous A/D convert start trigger generator - Emergency protective ...
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... Block Diagram I-Code Cortex-M3 CPU D-Code System Debug NVIC ROM for VE VE PMD PMD ADC ADC AMP/CMP (4ch) ENC (2ch) Fig1.1 TMPM370FYDFG/ FYFG block diagram I/F NANO FLASH I/F RAM I/F BOOT ROM Bus Bridge CG PLL WDT OFD r On_chip oscillato ...
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... Pin Layout and Pin Functions This chapter describes the pin layout, pin names and pin functions of TMPM370FYFG/TMPM370FYDFG. 2.1 Pin Layout (Top view) DVSS 1 INT3/TB0IN/PA0 TB0OUT/PA1 INT4/TB1IN/PA2 TB1OUT/PA3 5 CTS1/SCLK1/PA4 TB6OUT/TXD1/PA5 TB6IN/RXD1/PA6 INT8/TB4IN/PA7 TXD0/PE0 10 RXD0/PE1 CTS0/SCLK0/PE2 TB4OUT/PE3 DVDD5 INT5/TB2IN/PE4 15 TB2OUT/PE5 INT6/TB3IN/PE6 INT7/TB3OUT/PE7 DVSS ...
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... INT5/TB2IN/PE4 TB2OUT/PE5 INT6/TB3IN/PE6 INT7/TB3OUT/PE7 20 DVSS INTB/PL0 INTA/PL1 UO0/PC0 XO0/PC1 25 VO0/PC2 YO0/PC3 WO0/PC4 ZO0/PC5 EMG0/PC6 30 Fig 2-2 Pin layout (TMPM370FYDFG) TMPM370FYDFG 100 pin(14x20) (Top View) Pin layout and pin function TMPM370 2-2 TMPM370 80 PJ2/AINB5 PJ3/AINB6 PJ4/AINB7 PJ5/AINB8 PJ6/AINB9/INTC 75 PJ7/AINB10/INTD PK0/AINB11/INTE PK1/AINB12/INTF PB7/TRST ...
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Pin function Table2.1 shows the pin functions of TMPM370FYFG/FYDFG. Table 2.2 shows the operating voltage of each pin, and table 2.3 shows the voltage range of every pin. Pin name Output during Reset CVREFD CVREFABC DVSS PA0 TB0IN/INT3 PA1 ...
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Table 2.1 Pin functions (2/5) Pin name Output during Reset PL0 Hi-Z INTB PL1 Hi-Z INTA PC0 Hi-Z UO0 PC1 Hi-Z XO0 PC2 Hi-Z VO0 PC3 Hi-Z YO0 PC4 Hi-Z WO0 PC5 Hi-Z ZO0 PC6 Hi-Z EMG0 PC7 Hi-Z OVV0 ...
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Table 2.1 Pin functions (3/5) Pin name Output during Reset PG3 Hi-Z YO1 PG4 Hi-Z WO1 PG5 Hi-Z ZO1 PG6 Hi-Z EMG1 PG7 Hi-Z OVV1 X1 DVSS Hi-Z X2 PF0 TB7IN Pull UP BOOT PF1 Hi-Z TB7OUT PF2 ENCA1 Hi-Z ...
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Table 2.1 Pin functions (4/5) Pin name Output during Reset PB7 Pull UP TRST PK1 AINB12 Hi-Z INTF PK0 AINB11 Hi-Z INTE PJ7 AINB10 Hi-Z INTD PJ6 AINB9 Hi-Z INTC PJ5 Hi-Z AINB8 PJ4 Hi-Z AINB7 PJ3 Hi-Z AINB6 PJ2 ...
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Pin name Output during Reset PH3 Hi-Z AINA3 PH2 AINA2 Hi-Z INT2 PH1 AINA1 Hi-Z INT1 PH0 AINA0 Hi-Z INT0 AMPVSS AMPVDD5 Table 2.2 Operating voltage of each Pin Pin name X1,X2 RESET MODE CVREFABC, CVREFD I/O (PAx,PCx-PGx,PLx) I/O(PBx) AIN(PHx-PKx) ...
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Processor Core 3.1 Processor Core The TX03 series has a high-performance 32-bit processor core (the ARM Cortex-M3 processor core). For information on the operations of this processor core, please refer to the “Cortex-M3 Technical Reference Manual” issued by ARM ...
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Exclusive access The DCode bus and the system bus of TMPM370FY are not support EXCLUSIVE ACCESS. 3.6 Reset operation 3.6.1 Initial state The internal circuits, register settings and pin status are undefined right after the power-on. The state continues ...
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Dubug Interface 4.1 Specification Overview The TMPM370 contains the Serial Wire JTAG Debug Port (SWJ-DP) unit for interfacing with the Debug Interface and the Embedded Trace Macrocell output to the dedicated pins (TRACEDATA[0]-[1], SWV) via the on-chip Trace Port ...
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The table 4-2 below summarizes the debug interface pin functions and related port settings after reset. Table 4-2 Debug interface pins and port setting after reset Initial PORT Debug ...
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Table 4-3 Debug Interface Usag JTAG+SW (After RESET) ------------------ JTAG+SW (No TRST ) JTAG+TRACE SW SW+SWV Disable Debug function ○：Enable、×：Disable (Can use general purpose port) 4.8 Peripherals operation during HALT mode (one time stop of running program) When Break during ...
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Memory Map The memory maps for the TMPM370FY are based on the ARM Cortex-M3 processor core memory map. The internal ROM, internal RAM and internal I/O regions of the TMPM370FY are mapped to the code, SRAM and peripheral regions ...
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Memory Map Fig 5-1 shows the memory map of the TMPM370FY. Single chip mode 0xFFFF FFFF Vendor Specific 0xE010 0000 0xE00F FFFF CPU Register Region 0xE000 0000 0x41FF FFFF Internal IO 0x4000 0000 0x2000 27FF Internal RAM (10K) 0x2000 ...
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Clock/Mode Control 6.1 Features The clock/mode control block enables to select clock gear, prescaler clock and warm-up of the PLL (including clock multiplication circuit) and oscillator. The low power consumption mode can reduce power consumption. This chapter describes how ...
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Registers 6.2.1 Register List Table 6-1 shows registers and addresses of the clock generator. System control register Oscillation control register Standby control register PLL selection register System clock selection register Table 6-1 Registers of Clock Generator Register name CGSYSCR ...
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Detailed Description of Registers 6.2.2.1 System Control Register (CGSYSCR) 7 Bit symbol - Read/Write After reset 0 Function 15 Bit symbol - Read/Write After reset 0 Function 23 Bit symbol - Read/Write After reset 0 Function 31 Bit symbol ...
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Oscillation Control Register (CGOSCCR) 7 Bit symbol - Read/Write R After reset 0 Function “0” is read. 15 Bit symbol WUODR1 Read/Write R/W After reset 0 Function Write “00”. 23 Bit symbol WUODR5 Read/Write After reset 0 Function Bit5:2 ...
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Standby Control Register (CGSTBYCR) 7 Bit symbol - Read/Write After reset 0 Function 15 Bit symbol - Read/Write After reset 0 Function 23 Bit symbol - Read/Write After reset 0 Function 31 Bit symbol - Read/Write After reset 0 ...
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PLL Selection Register (CGPLLSEL) 7 Bit symbol - Read/Write After reset 0 Function 15 Bit symbol - Read/Write After reset 1 Function 23 - Bit symbol Read/Write 0 After reset Function 31 - Bit symbol Read/Write 0 After reset ...
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System Clock Selection Register (CGCKSEL) 7 Bit symbol - Read/Write After reset 0 Function 15 Bit symbol - Read/Write After reset 0 Function 23 Bit symbol - Read/Write After reset 0 Function 31 Bit symbol - Read/Write After reset ...
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Clock Control 6.3.1 Clock System Block Diagram Fig.6-1 shows the clock system diagram. Each clock is defined as follows. fosc : Clock input from high-speed oscillator (X1 and X2) fpll : Clock octupled by PLL fc : Clock specified ...
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CGOSCCR<PLLON> PLL fosc External fosc oscillator CGPLLSEL<PLLSEL> CGOSCCR<XEN1> (Note) The input clocks to selector shown with an arrow are set as default after reset. 6.3.3 Clock Multiplication Circuit (PLL) This circuit outputs the fpll clock that is octuple of the ...
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How to configure the warm-up function Specify the count up clock for the warm-up counter in the CGOSCCR<WUPSEL1> bit. Write “0” to <WUPSEL1>. The warm-up time CGOSCCR<WUEON><WUEF> is used to confirm the start and completion of warm-up through software (instruction). ...
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System Clock The TMPM370 offers high-speed clock as system clock. The high-speed clock is dividable. • Input frequency from X1 and X2: 8MHz to 10MHz • Clock gear:1/1, 1/2, 1/4, 1/8, 1/16 (after reset: 1/1) Table 6-2 Range of ...
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Modes and Mode Transitions 6.4.1 Mode Transitions The NORMAL mode uses the high-speed clock for system clock. The IDLE and STOP modes can be used as the low power consumption mode that enables to reduce power consumption by halting ...
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Operation Modes As an operation mode, NORMAL is available. The features of NORMAL mode are described below. 6.5.1 NORMAL Mode This mode is to operate the CPU core and the peripheral hardware by using the high-speed clock ...
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IDLE Mode Only the CPU is stopped in this mode. Each peripheral function has one bit in its control register for enabling or disabling operation in the IDLE mode. When the IDLE mode is entered, peripheral functions for which ...
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Low power Consumption Mode Setting The low power consumption mode is specified by the setting of the standby control register CGSTBYCR<STBY2:0>. Table 6-4 shows the mode setting in the <STBY2:0>. Table 6-4 Low power consumption mode setting (Note) Do ...
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Releasing the Low Power Consumption Mode The low power consumption mode can be released by an interrupt request or reset. The release source that can be used is determined by the low power consumption mode selected. Details are shown ...
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Warm-up Mode transition requires the warm-up for stabilization of the internal circuit. In the mode transition from STOP to NORMAL, the warm-up counter is activated automatically. And then the system clock output is started after the elapse of configured ...
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Clock Operations in Mode Transition The clock operations in mode transition are described in the following section. 6.6.7.1 Transition of operation modes: NORMAL→STOP→NORMAL When returning to NORMAL mode from STOP mode, the warm-up is activated automatically necessary ...
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Exceptions This chapter describes features, types and handling of exceptions. Exceptions have close relation to the CPU core. Refer to “Cortex-M3 Technical Reference Manual” if needed. 7.1 Overview An exception causes the CPU to stop the currently executing process ...
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Handling Flowchart The following shows how an exception/interrupt is handled. In the following descriptions, indicates hardware handling. Each step is described later in this chapter. Processing Detection by CG/CPU Handling by CPU Branch to ISR Execution of ISR Return ...
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Exception Request and Detection (1) Exception occurrence Exception sources include instruction execution by the CPU, memory accesses, and interrupt requests from external interrupt pins or peripheral functions. An exception occurs when the CPU executes an instruction that causes an ...
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No Exception type １ Reset Non-Maskable 2 Interrupt 3 Hard Fault Memory 4 Management 5 Bus Fault 6 Usage Fault 7-10 Reserved 11 SVCall 12 Debug Monitor 13 Reserved 14 PendSV 15 SysTick 16- External Interrupt (Note 1) This product ...
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Priority groping The priority group can be split into groups. By setting the <PRIGROUP> of the application interrupt and reset control register, <PRI_n> can be divided into the pre-emption priority and the sub priority. A priority is compared with the ...
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Exception (Pre-emption) When an exception occurs, the CPU suspends the currently executing process and branches to the interrupt service routine. This is called “pre-emption”. (1) Stacking When the CPU detects an exception, it pushes the contents of the following ...
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Late-arriving If the CPU detects a higher priority exception before executing the ISR for a previous exception, the CPU handles the higher priority exception first. This is called “late-arriving”. A late-arriving exception causes the CPU to fetch a new ...
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Executing an ISR An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by the user. An ISR may need to include code for clearing the interrupt request so that the same interrupt will not occur ...
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Load current active interrupt number Loads the current active interrupt number from the stacked xPSR. The CPU uses this to track which interrupt to return to. Select SP If returning to an exception (Handler Mode SP_main. If returning ...
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Reset Exceptions Reset exceptions are generated from the following six sources. Use the Reset Flag (RSTFLG) Register of the Clock Generator to identify the source of a reset. ・External reset pin A reset exception occurs when an external reset ...
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SysTick SysTick provides interrupt features using the CPU’s system timer. When you set a value in the SysTick Reload Value Register and enable the SysTick features in the SysTick Control and Status Register, the counter loads with the value ...
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Interrupts This chapter describes routes, factors and required settings of interrupts. The CPU is notified of interrupts by the interrupt signal from each interrupt source. It sets priority on the interrupts and handles an interrupt request with the highest ...
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Generation An interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the NVIC’s Interrupt Set-Pending Register. ・From external pin Set the port control register so that the external pin ...
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List of Interrupt Sources Table 7-3 shows the list of interrupt sources. Table 7-3 List of Hardware Interrupt Sources (1/2) INT No INT0 Interrupt Pin (PH0/AINA0/96pin or 98pin) 0 INT1 Interrupt Pin (PH1/AINA1/95pin or 97pin) 1 INT2 Interrupt Pin ...
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Table 7-3 List of Hardware Interrupt Sources (2/2) No. INTTB30 16bit TMRB3 compare match detection 0/ Over flow 48 INTTB31 49 16bit TMRB3 compare match detection 1 INTCAP20 50 16bit TMRB2 input capture 0 INTCAP21 51 16bit TMRB2 input capture ...
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Interrupt handling 7.5.2.1 Flowchart The following shows how an interrupt is handled. In the following descriptions, Processing Settings for detection Settings for generating interrupt request signal Interrupt generation Not clearing standby mode Clearing standby mode CG detects interrupt (clearing ...
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Processing The CPU detects the interrupt. CPU detects interrupt The CPU handles the interrupt. CPU handles interrupt Program for the ISR. ISR Execution Clear the interrupt factor if needed. Returning to preceding Configure to return to the preceding program of ...
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Preparation When preparing for an interrupt needed to pay attention to the order of configuration to avoid any unexpected interrupt on the way. Initiating an interrupt or changing its configuration must be implemented in the following order ...
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You can assign grouping priority by using the PRIGROUP field in the Application Interrupt and Reset Control Register. ●NVIC register <PRI_n> <PRIGROUP> (Note) "n" indicates the corresponding exceptions/interrupts. This product uses three bits for assigning a priority level. （３）Preconfiguration 1 ...
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CGICRCG register. See “7.6.3.5 CGICRCG (CG Interrupt Clear Register)” for each value. Interrupt requests from external pins can be used without setting the clock generator if they are not used for exiting ...
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Detection by Clock Generator If an interrupt source is used for exiting a standby mode, an interrupt request is detected according to the active level specified in the clock generator, and is notified to the CPU. An edge-triggered interrupt ...
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If an interrupt source is set as level-sensitive, an interrupt request continues to exist until it is cleared at its source. Therefore, the interrupt source must be cleared. Clearing the interrupt source automatically clears the interrupt request signal from the ...
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Exception/Interrupt-related registers The CPU's NVIC registers and clock generator registers described in this chapter are shown below with their respective addresses. 7.6.1 Register List ●NVIC Resisters SysTick Control and Status Resister SysTick Reload Value Resister SysTick Current Value Resister ...
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NVIC Registers 7.6.2.1 SysTick Control and Status Register 7 bit Symbol Read/Write After reset Function 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 bit Symbol Read/Write After reset Function <bit0> <ENABLE> 1 ...
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SysTick Reload Value Register 7 bit Symbol Read/Write After reset Function 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 bit Symbol Read/Write After reset Function <bit23:0> <RELOAD> Set the value to load ...
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SysTick Current Value Register 7 bit Symbol Read/Write After reset Function [Read] Current SysTick timer value [Write] Clear 15 bit Symbol Read/Write After reset Function [Read] Current SysTick timer value [Write] Clear 23 bit Symbol Read/Write After reset Function ...
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SysTick Calibration Value Register 7 bit Symbol Read/Write After reset 1 Function 15 bit Symbol Read/Write After reset 0 Function 23 bit Symbol Read/Write After reset 0 Function 31 bit Symbol NOREF Read/Write R After reset 0 Function 0: ...
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Interrupt Set-Enable Register 1 7 bit Symbol Read/Write After reset 0 Function Interrupt number 7 [Write] 1: Enable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 15 [Write] 1: Enable [Read] 0: ...
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Interrupt Set-Enable Register 2 7 bit Symbol Read/Write After reset 0 Function Interrupt number 39 [Write] 1: Enable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 47 [Write] 1: Enable [Read] 0: ...
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Interrupt Set-Enable Register 3 7 bit Symbol Read/Write After reset 0 Function Interrupt number 71 [Write] 1: Enable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write 0 After reset Function “0” is read. 23 bit Symbol Read/Write 0 ...
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Interrupt Clear-Enable Register 1 7 bit Symbol Read/Write After reset 0 Function Interrupt number 7 [Write] 1: Disable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 15 [Write] 1: Disable [Read] 0: ...
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Interrupt Clear-Enable Register 2 7 bit Symbol Read/Write After reset 0 Function Interrupt number 39 [Write] 1: Disable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 47 [Write] 1: Disable [Read] 0: ...
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Interrupt Clear-Enable Register 3 7 bit Symbol Read/Write After reset 0 Function Interrupt number 71 [Write] 1: Disable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function “0” is read. 23 bit Symbol Read/Write After ...
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Interrupt Set-Pending Register 1 7 bit Symbol Read/Write After reset Function Interrupt Interrupt number 7 number 6 [Write] [Write] 1: Pend 1: Pend [Read] [Read] 0: Not 0: Not pending pending 1: Pending 1: Pending 15 bit Symbol Read/Write ...
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Use these bits to force interrupts into the pending state or determine which interrupts are currently pending. Writing “1” bit in this register pends the corresponding interrupt. However, writing “1” has no effect on an interrupt ...
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Interrupt Set-Pending Register 2 7 bit Symbol Read/Write After reset Function Interrupt Interrupt number 39 number 38 [Write] [Write] 1: Pend 1: Pend [Read] [Read] 0: Not 0: Not pending pending 1: Pending 1: Pending 15 bit Symbol Read/Write ...
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Use these bits to force interrupts into the pending state or determine which interrupts are currently pending. Writing “1” bit in this register pends the corresponding interrupt. However, writing “1” has no effect on an interrupt ...
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Interrupt Set-Pending Register 3 7 bit Symbol Read/Write After reset Function Interrupt number 71 [Write] 1: Pend [Read] 0: Not pending 1: Pending 15 bit Symbol Read/Write After reset Function “0” is read. 23 bit Symbol Read/Write After reset ...
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Interrupt Clear-Pending Register 1 7 bit Symbol Read/Write After reset Function Interrupt Interrupt number 7 number 6 [Write] [Write] 1: Clear 1: Clear pending pending interrupt interrupt [Read] [Read] 0: Not 0: Not pending pending 1: Pending 1: Pending ...
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Use these bits to clear pending interrupts or determine which interrupts are currently pending. Writing “1” bit in this register clears the corresponding pending interrupt. However, writing “1” has no effect on an interrupt that is ...
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Interrupt Clear-Pending Register 2 7 bit Symbol Read/Write After reset Function Interrupt Interrupt number39 number 38 [Write] [Write] 1: Clear 1: Clear pending pending interrupt interrupt [Read] [Read] 0: Not 0: Not pending pending 1: Pending 1: Pending 15 ...
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Use these bits to clear pending interrupts or determine which interrupts are currently pending. Writing “1” bit in this register clears the corresponding pending interrupt. However, writing “1” has no effect on an interrupt that is ...
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Interrupt Clear-Pending Register 3 7 bit Symbol Read/Write After reset Function Interrupt number 39 [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending 15 bit Symbol Read/Write After reset Function “0” is read. 23 bit Symbol Read/Write ...
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Interrupt Priority Registers Each interrupt is provided with eight bits of an Interrupt Priority Register. The following shows the addresses of the Interrupt Priority Registers corresponding to interrupt numbers. 31 0xE000_E400 PRI_3 0xE000_E404 PRI_7 0xE000_E408 PRI_11 0xE000_E40C PRI_15 0xE000_E410 ...
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Symbol Read/Write After reset Function Priority of interrupt number 0 15 bit Symbol Read/Write After reset Function Priority of interrupt number 1 23 bit Symbol Read/Write After reset Function Priority of interrupt number 2 31 bit Symbol Read/Write ...
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Vector Table Offset Register 7 bit Symbol TBLOFF Read/Write R/W After reset 0 Function Offset value 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 bit Symbol Read/Write After reset Function “0” is ...
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Application Interrupt and Reset Control Register 7 bit Symbol Read/Write After reset 0 Function 15 bit Symbol ENDIAN ESS Read/Write R/W After reset 0 Function Endiannes s bit 23 bit Symbol Read/Write After reset 0 Function Register key [Write] ...
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VECTKEY/ VECTSTAT (Note1) Little-endian is the default memory format for this product. (Note2) When SYSRESETREQ is output, warm reset is performed on this product. <SYSRESETREQ> is cleared by warm reset. 1: big endian 0: little endian Register key [Write] ...
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System Handler Priority Registers System Handler Priority Registers have eight bits per each exception. The following shows the addresses of the System Handler Priority Registers corresponding to each exception. 31 0xE000_ED18 PRI_7 0xE000_ED1C PRI_11 (SVCall) 0xE000_ED20 PRI_15 (SysTick) The ...
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System Handler Control and State Register 7 bit Symbol SVCALL ACT Read/Write R/W After reset 0 Function SVCall 0: Inactive 1: Active 15 bit Symbol SVCALL PENDED Read/Write R/W After reset 0 Function SVCall 0: Not pended 1: Pended ...
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Extreme caution is needed to clear or set the active bits, because clearing and setting these bits does not repair stack contents. Set to “0” to disable or “1” to enable Memory Management. ...
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Clock Generator Registers 7.6.3.1 CG Interrupt Mode Control Register A This resister set the clearing standby request active level of external interrupt INT0 to INT3. 7 CGIMCGA bit Symbol Read/Write R After reset 0 “0” is read Active state ...
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CG Interrupt Mode Control Register B This resister set the clearing standby request active level of external interrupt INT4 to INT7. 7 CGIMCGB bit Symbol Read/Write R After reset 0 “0” is read Active state setting of INT4 standby ...
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CG Interrupt Mode Control Register C This resister set the clearing standby request active level of external interrupt INT8 to INTB. 7 CGIMCGC bit Symbol Read/Write R After reset 0 Function “0” is read 15 bit Symbol Read/Write R ...
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CG Interrupt Mode Control Register D This resister set the clearing standby request active level of external interrupt INTC to INTF. 7 CGIMCGD bit Symbol Read/Write R After reset 0 “0” is read Active state setting of INTC standby ...
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Be sure to set active state of the Standby clear request, in case the interrupt is enabled for clearing the Standby modes. (Note 1) When using interrupts, be sure to follow the sequence of actions shown below the ...
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CG Interrupt Clear Request Register This resister clear the Interrupt request from INT0 to INTF. 7 CGICRCG bit Symbol Read/Write After reset Function “0” is read. 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset ...
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NMI Flag Register NMI Flag resister is a resister for reading NMI generation status. CGNMIFLG 7 bit Symbol Read/Write After reset 0 Function 15 bit Symbol Read/Write 0 After reset Function 23 bit Symbol Read/Write 0 After reset Function ...
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Reset Flag Register Reset Flag Resister is a resister for reading internal Reset generation status per generation factors. Since this register is not cleared automatically necceary to write “0” to clear the register. CGRSTFLG 7 bit Symbol ...
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Input/Output Ports 8.1 Port registers PxDATA : Port data register To read/write port data. PxCR : Output control Register To control enable/disable output enable/disable input, controled by PxIE register. PxFRn : Function control Register To set functions. ...
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Port Functions 8.2.1 Port States in Stop Mode Input and output in Stop mode are enabled/disabled by the CGSTBYCR<DRVE> bit in the Standby Control Register If PxIE or PxCR is enabled with <DRVE>=1, input or output is enabled respectively ...
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Port A (PA0 to PA7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port A performs the serial interface ...
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PA7F2 PAFR2 Bit Symbol (0x4000_000C) Read/Write After reset 0 Function 0:PORT 1 INT8 7 PA7OD PAOD Bit Symbol (0x4000_ 0028) Read/Write After reset 0 Function 7 PA7UP PAPUP Bit Symbol (0x4000_002C) Read/Write After reset 0 Function 7 PA7DN PAPDN ...
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Port B (PB0 to PB7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port B performs the debug communication ...
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PB7F1 PBFR1 Bit Symbol (0x4000_0048) Read/Write After reset 1 Function 0:PORT 1:TRST 7 PB7OD PBOD Bit Symbol (0x4000_ 0068) Read/Write After reset 0 Function 7 PB7UP PBPUP Bit Symbol (0x4000_006C) Read/Write After reset 1 Function 7 PB7DN PBPDN Bit ...
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Port C (PC0 to PC7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the ports C perform the input/output port ...
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PC7OD PCOD Bit Symbol (0x4000_ 00A8) Read/Write After reset 0 Function 7 PC7UP PCPUP Bit Symbol (0x4000_00AC) Read/Write After reset 0 Function 7 PC7DN PCPDN Bit Symbol (0x4000_00B0 Read/Write After reset 0 Function 7 PC7IE PCIE Bit Symbol (0x4000_00B8) ...
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Port D (PD0 to PD6) The port general-purpose, 7-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port D performs the serial interface ...
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PDFR2 Bit Symbol (0x4000_00CC) Read/Write After reset Function 7 － PDOD Bit Symbol (0x4000_ 00E8) Read/Write R After reset 0 Function “0” is read PDPUP Bit Symbol (0x4000_00EC) Read/Write R After reset 0 Function “0” is ...
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Port E (PE0 to PE7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port E performs the serial interface ...
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PE7F2 PEFR2 Bit Symbol (0x4000_010C) Read/Write R/W After reset 0 Function 0:PORT 1:INT7. 7 PE7OD PEOD Bit Symbol (0x4000_ 0128) Read/Write After reset 0 Function 7 PE7UP PEPUP Bit Symbol (0x4000_012C) Read/Write After reset 0 Function 7 PE7DN PEPDN ...
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Port F (PF0 to PF4) The port general-purpose, 5-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port F performs the functions of ...
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PFFR3 Bit Symbol (0x4000_0150) Read/Write After reset Function 7 － PFOD Bit Symbol (0x4000_0168) Read/Write After reset Function 7 － PFPUP Bit Symbol (0x4000_016C) Read/Write After reset Function 7 － PFPDN Bit Symbol (0x4000_0170) Read/Write After reset Function ...
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Port G (PG0 to PG7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port G performs the input/output port ...
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PG7OD PGOD Bit Symbol (0x4000_01A8) Read/Write After reset 0 Function 7 PG7UP PGPUP Bit Symbol (0x4000_01AC) Read/Write After reset 0 Function 7 PG7DN PGPDN Bit Symbol (0x4000_01B0) Read/Write After reset 0 Function 7 PG7IE PGIE Bit Symbol (0x4000_01B8) Read/Write ...
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Port H (PH0 to PH7) The port general-purpose 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port H performs the analog input ...
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PH7OD PHOD Bit Symbol (0x4000_ 01E8) Read/Write After reset 0 Function 7 PH7UP PHPUP Bit Symbol (0x4000_01EC) Read/Write After reset 0 Function 7 PH7DN PHPDN Bit Symbol (0x4000_01F0) Read/Write After reset 0 Function 7 PH7IE PHIE Bit Symbol (0x4000_01F8) ...
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Port I (PI0 to PI3) The port general-purpose, 4-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port I performs the analog input ...
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PIPDN Bit Symbol (0x4000_0230) Read/Write After reset 0 Function 7 － PIIE Bit Symbol (0x4000_0238) Read/Write After reset 0 Function Port I pull-down control register － － － “0” is read ...
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Port J (PJ0 to PJ7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port J performs the analog input ...
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PJ7OD PJOD Bit Symbol (0x4000_ 0268) Read/Write After reset 0 Function 7 PJ7UP PJPUP Bit Symbol (0x4000_026C) Read/Write After reset 0 After reset 7 PJ7DN PJPDN Bit Symbol (0x4000_0270) Read/Write After reset 0 After reset 7 PJ7IE PJIE Bit ...
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Port K (PK0 to PK1) The port general-purpose, 2-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port K performs the functions as ...
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PKOD Bit Symbol (0x4000_ 02A8) Read/Write After reset 0 Function 7 － PKPUP Bit Symbol (0x4000_02AC) Read/Write After reset 0 Function 7 － PKPDN Bit Symbol (0x4000_02B0) Read/Write After reset 0 Function 7 － PKIE Bit Symbol (0x4000_02B8) ...
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Port L(PL0 to PL1) The port general-purpose, 2-bit input port. For this port, inputs can be specified in units of bits. Besides the general-purpose input function, the port L performs the functions as the external interrupt ...
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Block Diagrams of Ports 8.3.1 Port Types The ports are classified into 21 types shown below. Please refer to the following pages for the block diagrams of each port type. Type Port Function1 Function2 Function3 Analog T1 i/o o ...
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Type T1 Type general-purpose input/output port with pull-up and pull-down used to output function data as well. The function output is controlled by an enable signal. If enabled, the function data is output. PxUP ...
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Type T2 Type general-purpose input/output port with pull-up and pull-down used to output function data as well. PxUP PxDN PxCR 内 部 デ PxFR1 ー タ バ Function output1 機能出力 1 ス PxDATA PxOD ...
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Type T3 Type general-purpose input/output port with pull-up and pull-down used to input function data as well. PxUP PxDN PxCR 内 部 デ ー PxFR1 タ バ ス PxDATA PxOD PxIE Port read ポートリード ...
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Type T4 Type general-purpose input/output port with pull-up and pull-down used to output function data and interrupt input as well. PxUP PxDN PxCR 内 部 PxFR1 デ ー タ バ PxDATA ス PxOD PxIE ...
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Type T5 Type general-purpose input/output port used to interrupt input as well. PxFR1 内 部 デ ー タ バ PxIE ス Port read ポートリード Interrupt 割り込み入力 input Drive disable in STOP 時のドライブ禁止 Stop mode ...
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Type T6 Type general-purpose port with pull-up used to output function data and input interrupt as well. The function output is controlled by an enable signal. If enabled, the function data is output. PxUP ...
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Type T7 Type general-purpose input/output port with pull-up used to input function data as well. PxUP PxCR 内 部 デ PxFR1 ー タ バ ス PxDATA PxIE ポートリード Port read 機能入力 1 Function input1 ...
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Type T8 Type general-purpose input/output port with pull-down used to input function data as well. PxDN PxCR 内 部 デ PxFR1 ー タ バ PxDATA ス PxIE Port read ポートリード 機能入力 1 Function input1 ...
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Type T9 Type general-purpose input/output port with pull-up and pull-down used to output function data and two input function data as well. PxUP PxDN PxCR 内 PxFR1 部 デ PxFR2 ー タ Function output1 ...
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Type T10 Type T10 is a general-purpose input/output port with pull-up and pull-down used to output function data and input function data as well. PxUP PxDN PxCR 内 PxFR1 部 デ PxFR2 ー タ 機能出力 1 バ ...
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Type T11 Type T11 is a general-purpose input/output port with pull-up and pull-down used to two input function data as well. PxUP PxDN PxCR 内 PxFR1 部 デ PxFR2 ー タ バ PxDATA ス PxOD PxIE Port ...
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Type T12 Type T12 is a general-purpose input/output port with pull-up and pull-down used to input function data and interrupt input as well. PxUP PxDN PxCR 内 部 PxFR1 デ ー PxFR2 タ バ ス PxDATA PxOD ...
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Type T13 Type T13 is a general-purpose input/output port with pull-up and pull-down used to two output function data as well. PxUP PxDN PxCR PxFR1 内 PxFR2 部 デ ー Function input 2 機能出力 2 タ 機能出力 ...
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Type T14 Type T14 is a general-purpose input/output port with pull-up and pull-down used to output function data and interrupt input as well. PxUP PxDN PxCR PxFR1 内 部 PxFR2 デ ー Function output 1 機能出力 1 ...
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Type T15 Type T15 is a general-purpose input/output port with pull-up and pull-down used to output function data and three input function data as well. PxUP PxDN PxCR PxFR1 内 部 PxFR2 デ ー PxFR3 タ バ ...
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Type T16 Type T16 is a general-purpose input/output port with pull-up and pull-down used to input analog signals for A/D converter as well. PxUP PxDN PxCR 内 部 デ ー タ バ PxDATA ス PxOD PxIE Port ...
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Type T17 Type T17 is a general-purpose input/output port with pull-up and pull-down used to input analog signals for A/D converter and interrupt input as well. PxUP PxDN PxCR 内 部 PxFR1 デ ー タ バ PxDATA ...
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Type T18 Type T18 is a general-purpose input/output port with pull-up used to output function data as well. PxUP PxCR 内 部 PxFR1 デ ー タ 機能出力 1 Function output1 バ ス PxDATA PxIE Port read ポートリード ...
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Type T19 Type T19 is a general-purpose port with pull-up used to output function data as well. The function output is controlled by an enable signal. If enabled, the function data is output. PxUP PxCR 機能出力許可 Function ...
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Type T20 Type T20 is a general-purpose input/output port with pull-up and pull-down used to input function data as well. During reset, it functions as an input port for a BOOT signal. PxUP PxDN PxCR 内 部 ...
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Timer/Event Counters (TMRBs) 9.1 Outline TMPM370 have the eight channels multi-functional 16-bit timer/event counter. (TMRB0 through TMRB7) TMRBs operate in the following four operation modes: • 16-bit interval timer mode • 16-bit event counter mode • 16-bit programmable ...
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Specification differences among channels Channels (TMRB0 through TMRB7) operate independently and the functions are same except the differences as shown in Table 9-1 and Table 9-2. Therefore, the operational descriptions here are explained only for TMRB0. Table 9-1 Differences ...
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Configuration Each channel consists of a 16-bit up-counter, two 16-bit timer registers (one of which is double-buffered), two 16-bit capture registers, two comparators, a capture input control, a timer flip-flop and its associated control circuit. Timer operation modes and ...
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Registers 9.4.1 TMRB registers Table 9-3 shows the register names and addresses of each channel. Channel Specification Timer enable register TB0EN Timer RUN register TB0RUN 0x4001_0004 TB1RUN 0x4001_0044 TB2RUN 0x4001_0084 TB3RUN 0x4001_00C4 Timer control register TB0CR Timer mode register ...
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TMRBn enable register (channels 0 through 7) 31 TBnEN bit Symbol (0x4001_0xx0) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol TBnEN Read/Write R/W ...
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TMRB RUN register (channels 0 through 7) 31 bit Symbol TBnRUN (0x4001_0xx4) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol Read/Write After reset ...
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TMRB control register (channels 0 through 7) 31 bit Symbol TBnCR (0x4001_0xx8) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol TBnWBF Read/Write R/W ...
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TMRB mode register (channels 0 thorough 7) 31 TBnMOD bit Symbol (0x4001_0xxC) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R 0 After reset 7 bit Symbol Read/Write R After ...
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Controls the timing to write to timer registers 0 and 1 when double buffering is enabled. 0: The data transfer to the timer register 0 and 1 is done by corresponding to the up-counter (UC) regardless of the rewriting ...
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TMRB flip-flop control register (channels 0 through 7) 31 bit Symbol TBnFFCR (0x4001_0xx0) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol Read/Write After ...
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TMRB status register (channels 0 through 7) 31 bit Symbol TBnST (0x4001_0xx4) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol Read/Write After reset ...
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TMRB interrupt mask register (channels 0 through 7) 31 TBnIM bit Symbol (0x4001_0xx8) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol Read/Write After ...
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TMRB read capture register (channels 0 through 7) 31 TBnUC0 bit Symbol (0x4001_0xxC) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 UCn15 bit Symbol Read/Write After reset Function 7 UCn7 bit Symbol Read/Write ...
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TMRB timer register (channels 0 through 7) 31 TBnRG0 bit Symbol (0x4001_0xx0) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol TBnRG015 Read/Write After reset Function 7 bit Symbol TBnRG07 Read/Write After ...
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TMRB capture register (channels 0 through 7) 31 bit Symbol TBnCP0 (0x4001_0xx8) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol TBnCP015 Read/Write After reset Function 7 bit Symbol TBnCP07 Read/Write After ...
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Description of Operations for Each Circuit The channels operate in the same way, except for the differences in their specifications as shown in Table 9-1 and Table 9-2 . Therefore, the operational descriptions here are only for channel 0. ...
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Table 9-4 Prescaler Output Clock Resolutions @fc = 80MHz Clear peripheral Clock gear Prescaler clock clock value selection <FPSEL> <GEAR2:0> <PRCK2:0> 000(fperiph/1) 001(fperiph/2) 010(fperiph/4) 000 (fc) 011(fperiph/8) 100(fperiph/16) fc/2 101(fperiph/32) fc/2 000(fperiph/1) 001(fperiph/2) 010(fperiph/4) 100(fc/2) 011(fperiph/8) 100(fperiph/16) fc/2 101(fperiph/32) fc/2 ...
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The prescaler output clock φTn must be selected as φTn<fsys. (φTn is slower than (Note 1) fsys). (Note 2) Do not change the clock gear while the timer is operating. (Note 3) “⎯“ denotes a setting prohibited. 16-bit Timer/Event Counters ...
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Up-counter (UC 16-bit binary counter. • Source clock UC source clock, specified by types φT1, φT4 and φT16 of prescaler output clock or the external clock of the TB0IN pin. • Count start/ stop Counter operation ...
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Timer registers (TB0RG0, TB0RG1) TB0RG0 and TB0RG1 are registers for setting values to compare with up-counter values and two registers are built into each channel. If the comparator detects a match between a value set in this timer register ...
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Capture Registers (TB0CP0, TB0CP1) These are 16-bit registers for latching values from the UC up-counter. To read data from the capture register, use a 16-bit data transfer instruction or read in the order of low-order bits followed by high-order ...
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Description of Operations for Each Mode 9.6.1 16-bit Interval Timer Mode -Generating interrupts at periodic cycles To generate the INTTB01 interrupt, specify a time interval in the TB0RG1 timer register. Same as TB0RG0, INTTB01 interrupt is generated by setting ...
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Programmable Square Wave Output Mode (PPG) Square waves with any frequency and any duty (programmable square waves) can be output. The output pulse can be either low-active or high-active. Programmable square waves can be output from the TB0OUT ...
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The block diagram of this mode is shown below. Selector TB0IN0 φT1 φT4 φT16 Selector TB0RG0-WR TB0CR<TB0WBF> Fig. 9-4 Block Diagram of 16-bit PPG Mode Each register in the 16-bit PPG output mode must be programmed as listed below. 7 ...
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External trigger Programmable Square Wave Output Mode (PPG) Using an external count start trigger enables one-shot pulse generation with a short delay. (1) The 16-bit up-counter (UC) is programmed to count up on the rising edge of the TB0IN ...
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Application example using the Capture Function The capture function can be used to develop many applications, including those described below: One-shot pulse output triggered by an external pulse Pulse width measurement One-shot pulse output triggered by an external pulse ...
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If a delay is not required, TB0FF0 is reversed when data is taken into TB0CP0, and TB0RG1 is set to the sum of the TB0CPO value (c) and the one-shot pulse width (p p), by generating the INTTB00 ...
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Pulse width measurement By using the capture function, the “H” level width of an external pulse can be measured. Specifically, by putting free-running state using the prescaler output clock, an external pulse is input through the TB0IN ...
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Serial Channel (SIO) 10.1 Features This device has four serial I/O channels: SIO0 to SIO3. Each channel operates in either the UART mode (asynchronous communication) or the I/O interface mode (synchronous communication) which is selected by the user. I/O ...
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Table 10-1 Difference in the Specifications of SIO Modules Pin name Interrupt In the UART mode, TMRB output to use for the serial transfer clock Enable register Transmit/ receive buffer register Control register Mode control register 0 Baud rate generator ...
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Mode 0 (I/O Interface mode) /LSB first bit Transmission direction • Mode 0 (I/O Interface mode) /MSB first bit Transmission direction • Mode 1 (7 bits UART mode) Without parity start ...
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Block Diagram (Channel 0) Prescaler φ φT1 φT4 Serial clock generation circuit SC0BRCR <BR0CK1, 0> SC0BRCR <BR0S3: 0> φT1 φT4 φT16 φT64 Baud rate generator f /2 SYS SCLK0 input (shared with PE2) ...
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Operation of Each Circuit (Channel 0) 10.3.1 Prescaler The device includes a 7-bit prescaler to generate necessary clocks to drive SIO0. The input clock φT0 to the prescaler is selected by SYSCR1 of CG <PRCK2:0> to provide the frequency ...
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Table 10-2 Clock Resolution to the Baud Rate Generator Clear peripheral Clock gear Prescaler clock clock value selection <FPSEL> <GEAR2:0> <PRCK2:0> 000(fperiph/1) 001(fperiph/2) 010(fperiph/4) 000 (fc) 011(fperiph/8) 100(fperiph/16) fc/2 101(fperiph/32) fc/2 000(fperiph/1) 001(fperiph/2) 010(fperiph/4) 100(fc/2) 011(fperiph/8) 100(fperiph/16) fc/2 101(fperiph/32) fc/2 ...
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The prescaler output clock φTn must be selected so that the relationship “φTn < fsys” is satisfied (so that φTn is slower than fsys). (Note 2) Do not change the clock gear while SIO is operating. (Note 3) ...
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Baud Rate Generator The baud rate generator generates transmit and receive clocks to determine the serial channel transfer rate. The baud rate generator uses either the φT1, φT4, φT16 or φT64 clock supplied from the 7-bit prescaler. This input ...
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Example baud rate setting: 1) Division by an integer (divide by N): Selecting fc = 78.642 MHz for fperiph, setting φT0 to fperiph/16, using the baud rate generator input clock φT1, setting the divide ratio N (SC0BRCR<BR0S3:0> ...
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Baud rate calculation for an external clock input: 1) UART mode Baud Rate = external clock input / 16 In this, the period of the external clock input must be greater than 2/fsys. The highest baud rate must be ...
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Table 10-3 Selection of UART Baud Rate (Using the baud rate generator with SC0BRCR <BR0ADDE> [MHz] Divide ratio N (Set to SC0BRCR <BR0S3 : 0>) 9.830400 2 ↑ 4 ↑ 8 ↑ 16 (Note) This table shows ...
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Serial Clock Generation Circuit This circuit generates basic transmit and receive clocks. • I/O interface mode In the SCLK output mode with the SC0CR <IOC> serial control register set to “0,” the output of the previously mentioned baud rate ...
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The CPU will read the data from either the second receive buffer (SC0BUF) or from the receive FIFO (the address is the same as that of the receive buffer). If the receive FIFO has not been enabled, the receive buffer ...
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SC0MOD0 <WU> to “1.” In this case, the interrupt INTRX0 will be generated only when SC0CR <RB8> is set to “1.” 10.3.7 Receive FIFO Buffer In addition to the double buffer function already described, data may ...
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I/O interface mode with SCLK input: The following example describes the case a 6-byte data stream is received: SC0MOD1<6:5>=01: Transfer mode is set to half duplex mode. SC0FCNF <1:0> = 10101: Automatically allows continued reception after reaching the fill level. ...
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Transmit Counter The transmit counter is a 4-bit binary counter and is counted by SIOCLK as in the case of the receive counter. In UART mode, it generates a transmit clock (TXDCLK) on every 16th clock pulse. SIOCLK 15 ...
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Handshake function The CTS pin enables frame by frame data transmission so that overrun errors can be prevented. This function can be enabled or disabled by SC0MOD0 <CTSE>. When the CTS pin is set to the “H” level, the ...
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Transmit Buffer The transmit buffer (SC0BUF dual structure. The double buffering function may be enabled or disabled by setting the double buffer control bit <WBUF> in serial mode control register 2 (SC0MOD2). If double buffering is ...
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Transmit FIFO Buffer In addition to the double buffer function already described, data may be stored using the transmit FIFO buffer. By setting <CNFG> of the SC0FCNF register and <FDPX1:0> of the SC0MOD1 register, the 4-byte transmit buffer can ...
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I/O interface mode with SCLK input (normal mode): SC0MOD1<6:5>=10: Transfer mode is set to half duplex mode. SC0FCNF <4:0> = 01001: Allows continued transmission after reaching the fill level. SC0TFC <1:0> = 00: Sets the interrupt to be generated at ...
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Parity Control Circuit If the parity addition bit <PE> of the serial control register SC0CR is set to “1,” data is sent with the parity bit. Note that the parity bit may be used only in the 7- or ...
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If Transmit Buffer 2 is disabled, the under-run flag <PERR> will not be set. This flag is set to “0” when it is read. Note) Changing the mode from I/O interface SCLK output mode to ...
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CPU, the bit is cleared to “0.” If <WBUF> is set to “0,” this bit is insignificant and must not be used as a status flag. 10.3.19 Configurations of Transmit/Receive Buffer Transmit buffer UART Receive buffer I/O Interface Transmit buffer ...
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Interrupt/Error Generation Timing RX Interrupts Fig. 10-10 shows the data flow of receive operation and the route of read. Fig. 10-10 Receive Buffer/FIFO Configuration Diagram Single Buffer / Double Buffer RX interrupts are generated at the time depends on ...
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Table 10-5 Receive Interrupt conditions in use of FIFO SC0RFC<RFIS> “0” "The fill level of FIFO" is equal to "the fill level of FIFO interruption generation." "The fill level of FIFO" is greater than or equal to "the fill level ...
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Writing FIFO Interrupt conditions are decided by the SC0TFC<TFIS> settings as described in Table 10-6. Table 10-6 Transmit Interrupt conditions in use of FIFO SC0TFC<TFIS> “0” "The fill level of FIFO" is equal to "the fill level of FIFO interruption ...
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Register Description (Only for Channel 0) The channel 0 registers are described here. Each register for all the channels operates in the same way. (Note) Do not modify any control register when data is being transmitted or received. 10.4.1 ...
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Control register 7 bit Symbol RB8 Read/Write R SC0CR After reset 0 Receive data bit 8 (For UART) Function th <RB8>: 9 bit of the received data in the 9 bits UART mode. <EVEN>: Selects even or odd parity. ...
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Mode control register 0 7 bit Symbol TB8 Read/Write SC0MOD0 After reset 0 Transmit data bit 8 Function th <TB8>: Writes the 9 <CTSE>: Controls handshake function. Setting “1” enables handshake function using <RXE>: Controls reception Set <RXE> after ...