TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 446

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

Address
Normal
commands
ID
-READ
Block erase
Auto page
programming
Protection bit
programming
Protection bit
erase
Block erase
(Note 1)
(Note 3)
(Note 2)
PA: Program page address (Set the fourth bus write cycle address for page programming operation)
(7)
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
Flash area
Flash area
Flash area
Flash area
[31:19]
Addr
Table 20-17 "Flash Memory Access from the Internal CPU" can also be used.
Address setting can be performed according to the "Normal bus write cycle address
configuration" from the first bus cycle.
"0" is recommended" can be changed as necessary.
Block selection (Table 20-19)
Block selection (Table 20-19)
BA: Block address (Set the sixth bus write cycle address for block erase operation)
BA: Block address (Set the sixth bus write cycle address for block erase operation)
Address bit configuration for bus write cycles
Table 20-18 Address Bit Configuration for Bus Write Cycles
IA: ID address (Set the fourth bus write cycle address for ID-Read operation)
Protection bit selection
Addr
(Table 20-21)
Protection bit
[18]
“0” is recommended.
“0” is recommended.
selection
(Table 20-20)
Addr
[17]
Normal bus write cycle address configuration
Addr
[16]
Page selection
TMPM370 20-54
Addr
[15]
ID address
“0” is recommended.
Addr
[14]
Fixed to “0”.
[13:11]
Addr
Addr[1:0]=“0” (fixed) , Others:0 (recommended)
Addr[1:0]=“0” (fixed) , Others:0 (recommended)
Command
Addr[1:0]=“0” (fixed) , Others:0 (recommended)
(Table 20-20)
(Table 20-21)
Addr
Protection bit
Protection bit
[10]
selection
selection
Flash Memory Operation
Addr
[9]
Addr
[8]
Others:0 (recommended)
Others:0 (recommended)
Others:0 (recommended)
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
(recommended)
TMPM370
Others:0
[7:0]
Addr