TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 231

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

12.2 Control
Oscillation frequency detection control register 1
Oscillation frequency detection control register 2
(0x4004_0800)
(0x4004_0804)
(OFDCR2). The detection frequency is specified by lower/higher detection frequency setting registers
(OFDMNPLLOFF, OFDMNPLLON, OFDMXPLLOFF and OFDMXPLLON). Writing to OFDCR2/OFDMN-
PLLOFF/OFDMNPLLON/OFDMXPLLOFF/OFDMXPLLON is controlled by oscillation frequency control
register 1 (OFDCR1).
The oscillation frequency detection is controlled by oscillation frequency detection control register 2
Note 1: Only "0x06" and "0xF9" is valid to OFDCR1. If other value than "0x06" and "0xF9" is written to OFDCR1, "0x06" is
Note 2: OFDCR1 is not initialized by an internal factor reset including oscillation frequency detection reset. To initialize this
Note 1: Only "0x00" and "0xE4" is valid to OFDCR2. Writing other value than "0x00" and "0xE4" to OFDCR2 is ignored.
Note 2: Writing to OFDCR2 is protected by setting "0x06" to OFDCR1 but reading from OFDCR2 is always enabled with-
Note 3: OFDCR2 is not initialized by an internal factor reset including oscillation frequency detection reset. To initialize this
OFDCR1
OFDCR2
written to OFDCR1 automatically.
registers, set the RESET pin (external factor reset) to the low level.
out setting of OFDCR1.
registers, set the RESET pin (external factor reset) to the low level.
Read/Write
Read/Write
Read/Write
Read/Write
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
After reset
After reset
After reset
After reset
Function
Function
0x06: Disabling of writing to OFDCR2/OFDMNPLLOFF/OFDMNPLLON/OFDMXPLLOFF/
0xF9: Enabling of writing to OFDCR2/OFDMNPLLOFF/OFDMNPLLON/OFDMXPLLOFF/
Others: Reserved (Note 1)
0x00: Disabling of oscillation frequency detection
0xE4: Enabling of oscillation frequency detection
Others: Reserved (Note 1)
CLKWEN7
CLKSEN7
R/W
R/W
7
0
OFDMXPLLON (Write disable code)
OFDMXPLLON (Write enable code)
7
0
CLKWEN6
CLKSEN6
R/W
R/W
6
0
6
0
TMPM370 12-3
CLKWEN5
CLKSEN5
R/W
R/W
5
0
5
0
CLKWEN4
CLKSEN4
R/W
R/W
4
0
4
0
31-8
31-8
R
R
0
0
-
-
CLKWEN3
CLKSEN3
R/W
R/W
3
0
3
0
Oscillation Frequency Detector (OFD)
CLKWEN2
CLKSEN2
R/W
R/W
2
1
2
0
CLKWEN1
CLKSEN1
R/W
R/W
1
1
1
0
CLKWEN0
CLKSEN0
R/W
R/W
TMPM370
0
0
0
0