TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 229

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

12. Oscillation Frequency Detector (OFD)
12.1 Configuration
clock OFDMNPLLexceeds the detection frequency range.
quency range is specified by OFDMNPLLOFF/OFDMNPLLON/OFDMXPLLOFF/OFDMXPLLON which
are the detection frequency setting registers. The lower detection frequency is specified by OFDMN-
PLLOFF/OFDMNPLLON registers and the higher detection frequency is specified by OFDMXPLLOFF/
OFDMXPLLON registers. An initial value of detection frequency is shown in Figure 12-1.
MXPLLOFF/OFDMXPLLON registers is disabled. Therefore, the setting the detection frequency to these
registers should be done when the oscillation frequency detection is disabled. And writing to OFDCR2/
OFDMNPLLOFF/OFDMNPLLON/OFDMXPLLOFF/OFDMXPLLON registers is controlled by OFDCR1
register. To write OFDCR2/OFDMNPLLOFF/OFDMNPLLON/OFDMXPLLOFF/OFDMXPLLON registers,
the write enable code "0xF9" should be set to OFDCR1 beforehand. To enable the oscillation frequency
detector, set "0xE4" to OFDCR2 after setting "0xF9" to OFDCR1. Since the oscillation frequency detection
is disabled after an external reset input, write "0xF9" to OFDCR1 and write "0xE4" to OFDCR2 register to
enable its function.
ters, all I/Os become high impedance by reset. In case of PLLOFF, OFDMNPLLOFF and OFDMXPLLOFF
registers are valid for detection and the setting value of OFDMNPLLON/OFDMXPLLON registers are
ignored. In case of PLLON, OFDMNPLLON and OFDMXPLLON registers are valid for detection and the
setting value of OFDMNPLLOFF/OFDMXPLLOFF registers are ignored. By the oscillation frequency
detection reset, all I/Os except power supply pins, RESET, X1 and X2 become high impedance. If oscilla-
tion frequency detection reset is generated by detecting the stopping of high frequency, the internal circu-
ities such as registers hold the condition at the timing of oscillation stop. To initialize these internal
circuitries, an external re-starting of oscillation is needed.
PLLON/ OFDMXPLLOFF/OFDMXPLLON) are not initialized by the reset generated from oscillation fre-
quency detector, the detection of oscillation is keeps its function during the reset period of oscillation
frequency detection. Therefore, if the oscillation frequency detection reset occurs, the reset is not
released unless the CPU clock resumes its normal frequency.
The oscillation frequency detector generates a reset for I/O if the oscillation of high frequency for CPU
The oscillation frequency detection is controlled by OFDCR1, OFDCR2 registers and the detection fre-
When the oscillation frequency detection is enabled, writing to OFDMNPLLOFF/OFDMNPLLON/OFD-
When the TMPM370 detects the out of frequency by lower and higher detection frequency setting regis-
Since all registers for oscillation frequency detector (OFDCR1/OFDCR2/OFDMNPLLOFF/OFDMN-
Note 1: The oscillation frequency detection reset is available only in NORMAL and IDLE modes. In STOP mode, the oscil-
Note 2: When the PLL is controlled (enabled or disabled) by the CGPLLSEL register, the OFD must be disabled before-
lation frequency detection reset is disabled automatically.
hand. If OFD reset is generated with PLL-ON, the detection frequency setting registers (OFDMNPLLON/OFDMX-
PLLON) are automatically switched over to OFDMNPLLOFF/OFDMXPLLOFF.
TMPM370 12-1
Oscillation Frequency Detector (OFD)
TMPM370