TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 274

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

Schedule Selection
0
1
4
9
output schedule handling output-related tasks and an input schedule handling input-related tasks. Table
15-5 shows the tasks that are executed in each schedule.
enable or disable zero-current detection as appropriate for each step of the motor control flow (see Table
15-6).
(VEACTSCH)
*1: Each task is executed only when it is specified.
*2: Phase interpolation
*3: Output OFF/EMGRS
*4: Task operation to be switched by zero-current detection
The VEACTSCH register is used to select the schedule to be executed. A schedule is comprised of an
The VEMODE register is used to enable or disable phase interpolation, control output operation, and
Speed control by current
Schedule 1
Schedule 4
Schedule 9
Individual
execution
Forced commutation
15.5.1.1
Motor Control Flow
EMG return
Positioning
Initial input
feedback
Brake
Stop
Current
control
Schedule Control
*1
－
－
computation
Schedule selection
Table 15-5 Tasks To Be Executed in Each Schedule
SIN/COS
(VEACTSCH)
*1
－
*2
*2
9
9
1
1
1
4
9
Table 15-6 Typical Setting Example
conversion
coordinate
Output
axis
Output Schedule
*1
－
Task specification
TMPM370 15-33
(VETASKAPP)
conversion
Output
phase
0
0
5
5
5
6
0
－
*1
Register Setting
Phase interpolation
Output
control
*1
(VEMODE)
*
*
*3
3
3
x
0
1
1
0
x
x
generation
Trigger
*1
Output control
processing
(VEMODE)
Input
*1
00
00
01
01
01
01
11
*4
*4
*
4
Input Schedule
Input phase
conversion
Vector Engine (VE)
－
*1
Zero-current
(VEMODE)
detection
TMPM370
0
1
0
0
0
0
0
conversion
coordinate
Input
axis
*1
－