TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 310

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

16.3.5 Dead Time Circuit
16.3.5.1 Dead Time Register (PMDnDTR)
and lower phases are switched to prevent a short circuit. The dead time is set to the Dead Time Register
(DTR) as an 8-bit value with a resolution of 100 ns at 80 MHz.
phases to be independently set through MDPOT<POLH> and <POLL>.
<DTR>: Dead time
Read/Write
Read/Write
Read/Write
Read/Write
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
The dead time circuit consists of a dead time unit and an output polarity switching unit.
The output polarity switching circuit allows the polarity (active high or active low) of the upper and lower
After reset
After reset
After reset
After reset
For each of the U, V and W phases, the ON delay circuit introduces a delay (dead time) when the upper
100 nsec × 8 bits (up to 25.5 μsec at fsys = 80 MHz)
*
Do not change this register while MDEN<PWMEN>=1.
R → 0
R → 0
R → 0
(PMD0:0x4005 0444, PMD1:0x4005 04C4)
31
23
15
0
0
0
7
0
-
-
-
fsys/8
w’
u’
x’
v’
y’
z’
R → 0
R → 0
R → 0
30
22
14
0
0
0
6
0
-
-
-
ON Delay Circuit
ON Delay Circuit
ON Delay Circuit
Figure 16-6 Dead Time Circuit
R → 0
R → 0
R → 0
29
21
13
0
0
0
5
0
-
-
-
TMPM370 16-26
PM DnDTR
R → 0
R → 0
R → 0
28
20
12
0
0
0
4
0
-
-
-
DTR
R/W
R → 0
R → 0
R → 0
<POLL>
MDPOT
27
19
11
0
0
0
3
0
-
-
-
<POLH>
M DPOT
R → 0
R → 0
R → 0
26
18
10
0
0
0
2
0
-
-
-
Motor control circuit
R → 0
R → 0
R → 0
25
17
Y
X
W
U
V
Z
0
0
9
0
1
0
-
-
-
R → 0
R → 0
R → 0
TMPM370
24
16
0
0
8
0
0
0
-
-
-