IDT82V2041EPP IDT, Integrated Device Technology Inc, IDT82V2041EPP Datasheet - Page 49
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IDT82V2041EPP
Manufacturer Part Number
IDT82V2041EPP
Description
IC LIU T1/J1/E1 1CH 44-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Line Interface Units (LIUs)r
Datasheet
1.IDT82V2041EPP8.pdf
(75 pages)
Specifications of IDT82V2041EPP
Protocol
E1
Voltage - Supply
3.13 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Number Of Transceivers
1
Screening Level
Industrial
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
82V2041EPP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V2041EPP
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V2041EPP8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V2041EPPG
Manufacturer:
IDT
Quantity:
351
Company:
Part Number:
IDT82V2041EPPG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V2041EPPG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Table-42 INTES: Interrupt Trigger Edge Select Register
Programming Information
IDT82V2041E
IBLBD_IES
IBLBA_IES
PRBS_IES
TCLK_IES
LOS_IES
AIS_IES
Symbol
DF_IES
-
(R/W, Address = 16H)
Bit
6
5
4
7
3
2
1
0
Default
0
0
0
0
0
0
0
0
Reserved
This bit determines the Inband Loopback Activate Code interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the IBLBA_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBA_S bit in STAT0
status register
This bit determines the Inband Loopback Deactivate Code interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the IBLBD_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBD_S bit in STAT0
status register
This bit determines the PRBS/QRSS synchronization status interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the PRBS_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the PRBS_S bit in STAT0
status register
This bit determines the TCLK Loss interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the TCLK_LOS bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the TCLK_LOS bit in STAT0
status register
This bit determines the Driver Failure interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the DF_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the DF_S bit in STAT0 status
register
This bit determines the AIS interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the AIS_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the AIS_S bit in STAT0 status
register
This bit determines the LOS interrupt event.
= 0: Interrupt is generated as a ‘0’ to ‘1’ transition of the LOS_S bit in STAT0 status register
= 1: Interrupt is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the LOS_S bit in STAT0 status
register
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
49
Description
December 9, 2005