IDT82V2041EPP IDT, Integrated Device Technology Inc, IDT82V2041EPP Datasheet - Page 24

• Manufacturer Part Number: IDT82V2041EPP
• Description: IC LIU T1/J1/E1 1CH 44-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2041EPP

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82V2041EPP

3.4.8
and RDN pin. In E1 mode, the RCLK outputs a recovered 2.048 MHz clock.
In T1/J1 mode, the RCLK outputs a recovered 1.544 MHz clock. The
received data is updated on the RD/RDP and RDN pins on the active edge
of RCLK. The active edge of RCLK can be selected by the RCLK_SEL bit
(RCF0, 0AH). And the active level of the data on RD/RDP and RDN can be
selected by the RD_INV bit (RCF0, 0AH).
selected. If RCLKE is set to high, the falling edge will be chosen as the active
edge of RCLK. If RCLKE is set to low, the rising edge will be chosen as the
active edge of RCLK. The active level of the data on RD/RDP and RDN is
the same as that in software control mode.
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 0AH). In Single
Rail mode, only RD pin is used to output data and the RDN/CV pin is used
to report the received errors. In Dual Rail Mode, both RDP pin and RDN pin
are used for outputting data.
R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data
Slicer will be output to the RDP/RDN pins directly, and the RCLK outputs
the exclusive OR (XOR) of the RDP and RDN. This is called receiver slicer
mode. In this case, the transmit path is still operating in Dual Rail mode.
3.4.9
0AH) to ‘1’. In this case, the RCLK, RD/RDP, RDN and LOS will be logic low.
ing RPD pin to high. Refer to
details.
Functional Description
IDT82V2041E
The receive path system interface consists of RCLK pin, RD/RDP pin
In hardware control mode, only the active edge of RCLK can be
The received data can be output to the system side in two different ways:
In the receive Dual Rail mode, the CDR unit can be by-passed by setting
The receive path can be powered down by setting R_OFF bit (RCF0,
In hardware control mode, receiver power down can be selected by pull-
RECEIVE PATH SYSTEM INTERFACE
RECEIVE PATH POWER DOWN
5 Hardware Control Pin Summary
for more
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
24
3.5
can be deployed in the transmit path or the receive path, and can also be
disabled. This is selected by the JACF[1:0] bits (JACF, 04H).
depth of FIFO can be selected by JA[1:0] pins. Refer to
Pin Summary
3.5.1
Figure-11. The FIFO is used as a pool to buffer the jittered input data, then
the data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits
(JACF, 04H). In hardware
by JA[1:0] pins. Refer to
sequently, the constant delay of the Jitter Attenuator will be 16 bits, 32 bits
or 64 bits. Deeper FIFO can tolerate larger jitter, but at the cost of increasing
data latency time.
6.8 Hz, as selected by the JABW bit (JACF, 04H). In T1/J1 applications,
the Corner Frequency of the DPLL can be 1.25 Hz or 5.00 Hz, as selected
by the JABW bit (JACF, 04H). The lower the Corner Frequency is, the longer
time is needed to achieve synchronization.
will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 1AH).
If the incoming data moves slower than the outgoing data, the FIFO will
underflow. This underflow is captured by the
some applications that are sensitive to data corruption, the JA limit mode
can be enabled by setting JA_LIMIT bit (JACF, 04H) to ‘1’. In the JA limit
mode, the speed of the outgoing data will be adjusted automatically when
the FIFO is close to its full or emptiness. The criteria of starting speed adjust-
ment are shown in Table-12. The JA limit mode can reduce the possibility
of FIFO overflow and underflow, but the quality of jitter attenuation is dete-
riorated.
There is one Jitter Attenuator in the IDT82V2041E. The Jitter Attenuator
In hardware
The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in
In E1 applications, the Corner Frequency of the DPLL can be 0.9 Hz or
When the incoming data moves faster than the outgoing data, the FIFO
Jittered Clock
Jittered Data
JITTER ATTENUATOR
JITTER ATTENUATION FUNCTION DESCRIPTON
for details.
control
Figure-11 Jitter Attenuator
W
mode, Jitter Attenuator position, bandwidth and the
5 Hardware Control Pin Summary
control
32/64/128
FIFO
DPLL
MCLK
mode, the depth of FIFO can be selected
R
JAUD_IS
De-jittered Data
De-jittered Clock
December 9, 2005
bit (INTS1, 1AH). For
5 Hardware Control
for details. Con-
RD/RDP
RDN
RCLK