ADAV801ASTZ Analog Devices Inc, ADAV801ASTZ Datasheet - Page 7

• Manufacturer Part Number: ADAV801ASTZ
• Description: IC CODEC AUDIO R-DVD 3.3V 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV801ASTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 102dB
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Adc/dac Resolution: 24b
• Interface Type: Serial (SPI)
• Mounting: Surface Mount
• Number Of Adc's: 2
• Number Of Dac's: 2
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 64
• Power Supply Type: Analog/Digital
• Sample Rate: 96KSPS
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV801EBZ - BOARD EVALUATION FOR ADAV801
• Lead Free Status / Rohs Status: Compliant

TIMING SPECIFICATIONS
Timing specifications are guaranteed over the full temperature and supply range.
Table 3.
Parameter
MASTER CLOCK AND RESET
SPI PORT
SERIAL PORTS
1
TEMPERATURE RANGE
Table 4.
Heading
Specifications Guaranteed
Functionality Guaranteed
Storage
The prefix x refers to I-, O-, IAUX-, or OAUX- for the full pin name.
MCLKI Frequency
XIN Frequency
RESET Low
CCLK High
CCLK Low
CIN Setup
CIN Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
Slave Mode
Master Mode
xBCLK High
xBCLK Low
xBCLK Frequency
xLRCLK Setup
xLRCLK Hold
xSDATA Setup
xSDATA Hold
xSDATA Delay
xLRCLK Delay
xSDATA Delay
xSDATA Setup
xSDATA Hold
1
Symbol
f
f
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
MCLK
XIN
RESET
CCH
CCL
CIS
CIH
CLS
CLH
COE
COD
COTS
SBH
SBL
SBF
SLS
SLH
SDS
SDH
SDD
MLD
MDD
MDS
MDH
Min
20
40
40
10
10
10
10
40
40
64 × f
10
10
10
10
10
10
10
Rev. A | Page 7 of 60
S
Min
−40
−65
Typ
12.288
27.0
Typ
25
Max
54
54
15
20
25
5
10
Max
+85
+150
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
To CCLK rising edge
From CCLK rising edge
To CCLK rising edge
From CCLK rising edge
From CLATCH falling edge
From CCLK falling edge
From CLATCH rising edge
To xBCLK rising edge
From xBCLK rising edge
To xBCLK rising edge
From xBCLK rising edge
From xBCLK falling edge
From xBCLK falling edge
From xBCLK falling edge
From xBCLK rising edge
From xBCLK rising edge
Unit
°C
°C
°C
ADAV801