ADAV801ASTZ Analog Devices Inc, ADAV801ASTZ Datasheet - Page 36

• Manufacturer Part Number: ADAV801ASTZ
• Description: IC CODEC AUDIO R-DVD 3.3V 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV801ASTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 102dB
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Adc/dac Resolution: 24b
• Interface Type: Serial (SPI)
• Mounting: Surface Mount
• Number Of Adc's: 2
• Number Of Dac's: 2
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 64
• Power Supply Type: Analog/Digital
• Sample Rate: 96KSPS
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV801EBZ - BOARD EVALUATION FOR ADAV801
• Lead Free Status / Rohs Status: Compliant

ADAV801
Receiver Buffer Configuration—Address 0001011 (0x0B)
Table 35. Receiver Buffer Configuration Register Bit Map
7
Reserved
Table 36. Receiver Buffer Configuration Register Bit Descriptions
Bit Name
RxBCONF5
RxBCONF4
RxBCONF3
RxBCONF[2:1]
RxBCONF0
Transmitter Control—Address 0001100 (0x0C)
Table 37. Transmitter Control Register Bit Map
7
Reserved
Table 38. Transmitter Control Register Bit Descriptions
Bit Name
TxVALIDITY
TxRATIO[2:0]
TxCLKSEL[1:0]
TxENABLE
6
Reserved
6
TxVALIDITY
Description
This bit is used to set or clear the VALIDITY bit in the AES3/S/PDIF transmit stream.
Determines the AES3/S/PDIF transmitter to AES3/S/PDIF receiver ratio.
Selects the clock source for the AES3/S/PDIF transmitter.
Enables the AES3/S/PDIF transmitter.
Description
If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit
interrupt is enabled only when there is a change in the start (ID) bit.
This bit determines whether Channel A and Channel B user bits are stored in the buffer together or separated
between A and B.
Defines the function of RxCSBINT.
Defines the user bit buffer.
Defines the user bit buffer size, if RxBCONF[2:1] = 01.
0 = Audio is suitable for digital-to-analog conversion.
1 = Audio is not suitable for digital-to-analog conversion.
000 = Transmitter to receiver ratio is 1:1.
001 = Transmitter to receiver ratio is 1:2.
010 = Transmitter to receiver ratio is 1:4.
101 = Transmitter to receiver ratio is 2:1.
110 = Transmitter to receiver ratio is 4:1.
00 = Internal Clock 1 is the clock source for the transmitter.
01 = Internal Clock 2 is the clock source for the transmitter.
10 = Recovered PLL clock is the clock source for the transmitter.
11 = Reserved.
0 = AES3/S/PDIF transmitter is disabled.
1 = AES3/S/PDIF transmitter is enabled.
0 = User bit interrupt is enabled in normal mode.
1 = If the DAT category is detected, the user bit interrupt is enabled only if there is a change in the start (ID) bit.
0 = User bits are stored together.
1 = User bits are stored separately.
0 = RxCSBINT are set when a new block of receiver channel status is read, which is 192 audio frames.
1 = RxCSBINT is set only if the first five bytes of the receiver channel status block changes from the previous
channel status block.
00 = User bits are ignored.
01 = Updates the second user bit buffer when the first user bit buffer is full.
10 = Formats the received user bits according to Byte 1, Bit 4 to Bit 7, of the channel status, if the PRO bit is set. If
the PRO bit is not set, formats the user bits according to the IEC60958-3 standard.
11 = Reserved.
0 = 384 bits with Preamble Z as the start of the buffer.
1 = 768 bits with Preamble Z as the start of the buffer.
5
RxBCONF5
5
TxRATIO2
4
RxBCONF4
4
TxRATIO1
Rev. A | Page 36 of 60
3
RxBCONF3
3
TxRATIO0
2
RxBCONF2
2
TxCLKSEL1
1
RxBCONF1
1
TxCLKSEL0
0
RxBCONF0
0
TxENABLE