ADAV801ASTZ Analog Devices Inc, ADAV801ASTZ Datasheet - Page 50

• Manufacturer Part Number: ADAV801ASTZ
• Description: IC CODEC AUDIO R-DVD 3.3V 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV801ASTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 102dB
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Adc/dac Resolution: 24b
• Interface Type: Serial (SPI)
• Mounting: Surface Mount
• Number Of Adc's: 2
• Number Of Dac's: 2
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 64
• Power Supply Type: Analog/Digital
• Sample Rate: 96KSPS
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV801EBZ - BOARD EVALUATION FOR ADAV801
• Lead Free Status / Rohs Status: Compliant

ADAV801
ADC Control Register 1—Address 1101110 (0x6E)
Table 116. ADC Control Register 1 Bit Map
7
AMC
Table 117. ADC Control Register 1 Bit Descriptions
Bit Name
AMC
HPF
PWRDWN
ANA_PD
MUTER
MUTEL
PLPD
PRPD
ADC Control Register 2—Address 1101111 (0x6F)
Table 118. ADC Control Register 2 Bit Map
7
Reserved
Table 119. ADC Control Register 2 Bit Descriptions
Bit Name
BUF_PD
MCD[1:0]
6
HPF
6
Reserved
High-pass filter enable.
ADC power-down.
ADC analog section power-down.
Mute ADC right channel.
Mute ADC left channel.
PGA left power-down.
PGA right power-down.
Reference buffer power-down control.
ADC master clock divider.
Description
ADC modulator clock.
Description
0 = ADC MCLK/2 (128 × f
1 = ADC MCLK/4 (64 × f
0 = Normal.
1 = HPF enabled.
0 = Normal.
1 = Power-down.
0 = Normal.
1 = Power-down.
0 = Normal.
1 = Muted.
0 = Normal.
1 = Muted.
0 = Normal.
1 = Power-down.
0 = Normal.
1 = Power-down.
0 = Normal.
1 = Power-down.
00 = Divide by 1.
01 = Divide by 2.
10 = Divide by 3.
11 = Divide by 1.
5
PWRDWN
5
Reserved
S
).
S
).
4
ANA_PD
4
BUF_PD
Rev. A | Page 50 of 60
3
MUTER
3
Reserved
2
MUTEL
2
Reserved
1
PLPD
1
MCD1
0
PRPD
0
MCD0