ADAV801ASTZ Analog Devices Inc, ADAV801ASTZ Datasheet - Page 21

• Manufacturer Part Number: ADAV801ASTZ
• Description: IC CODEC AUDIO R-DVD 3.3V 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV801ASTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 102dB
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Adc/dac Resolution: 24b
• Interface Type: Serial (SPI)
• Mounting: Surface Mount
• Number Of Adc's: 2
• Number Of Dac's: 2
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 64
• Power Supply Type: Analog/Digital
• Sample Rate: 96KSPS
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV801EBZ - BOARD EVALUATION FOR ADAV801
• Lead Free Status / Rohs Status: Compliant

write address pointer is useful for applications in which small
changes in the sample rate ratio between f
expected. The maximum decimation rate can be calculated
from the RAM word depth and the group delay as
for short group delay and
for long group delay.
The digital servo loop is essentially a ramp filter that provides
the initial pointer to the address in RAM and ROM for the start
of the FIR convolution. The RAM pointer is the integer output
of the ramp filter, and the ROM is the fractional part. The
digital servo loop must provide excellent rejection of jitter on
the f
f
the fractional part of the ramp output by the ratio of f
to dynamically alter the ROM coefficients when f
The digital servo loop is implemented with a multirate filter. To
settle the digital servo loop filter more quickly upon startup or a
change in the sample rate, a fast mode has been added to the
filter. When the digital servo loop starts up or the sample rate is
changed, the digital servo loop enters fast mode to adjust and
settle on the new sample rate. Upon sensing that the digital
servo loop is settling down to a reasonable value, the digital
servo loop returns to normal (or slow) mode.
During fast mode, the MUTE_IND bit in the Sample Rate
Converter Error register is asserted to let the user know that
clicks or pops might be present in the digital audio data. The
output of the SRC can be muted by asserting Bit 7 of the Group
S_OUT
S_IN
(512 − 16)/64 taps = 7.75
(512 − 64)/64 taps = 7
clock within 4.97 ps. The digital servo loop also divides
REG 0x76
and f
BIT[1:0]
Figure 33. Clock and Datapath Control on the SRC
S_OUT
clocks, as well as measure the arrival of the
OUTPUT
MCLK
SRC
SRC
SRC
INPUT
SRC
REG 0x77
BIT[4:3]
REG 0x00
BITS[1:0]
REG 0x62
BITS[7:6]
S_IN
ADC
AUXILIARY IN
PLAYBACK
DIR
and f
S_IN
S_OUT
> f
S_IN
are
S_OUT
/f
S_OUT
.
Rev. A | Page 21 of 60
Delay and Mute register until the SRC has changed to slow
mode. The MUTE_IND bit can be set to generate an interrupt
when the SRC changes to slow mode, indicating that the data is
being sample rate converted accurately.
The frequency responses of the digital servo loop for fast mode
and slow mode are shown in Figure 34. The FIR filter is a 64-tap
filter when f
f
starting address of the RAM address pointer and the ROM
address pointer from the digital servo loop at the start of the
f
decrementing its address by 1 for each tap, and the ROM
pointer increments its address by the (f
f
over, the convolution is completed.
The convolution is performed for both the left and right
channels, and the multiply accumulate circuit used for the
convolution is shared between the channels. The f
sample rate ratio circuit is used to dynamically alter the
coefficients in the ROM when f
calculated by comparing the output of an f
output of an f
If f
by more than two f
comparison. This is done to provide some hysteresis to prevent
the filter length from oscillating and causing distortion.
Figure 33 shows the detail of the SRC section. The SRC master
clock is expected to be equal to 256 times the output sample
rate. This master clock can be provided by four different clock
sources. The selection is set by the SRC and Clock Control
register (Address 0x00), and the selected clock source can be
divided using the same register.
S_OUT
S_OUT
S_IN
S_IN
> f
–100
–120
–140
–160
–180
–200
–220
. The FIR filter performs its convolution by loading in the
period. The FIR filter then steps through the RAM by
–20
–40
–60
–80
> f
S_OUT
0
0.01
Figure 34. Frequency Response of the Digital Servo Loop;
f
S_OUT
S_IN
is the X-Axis, f
or 2
S_OUT
, the sample rate ratio is updated, if it is different
S_IN
0.1
20
≥ f
counter. If f
for f
S_OUT
S_IN
S_OUT
1
SLOW MODE
S_OUT
and is (f
periods from the previous f
FREQUENCY (Hz)
≥ f
= 192 kHz, Master Clock is 30 MHz
10
S_OUT
S_IN
S_IN
S_IN
. Once the ROM address rolls
> f
/f
100
> f
S_OUT
S_IN
S_OUT
S_OUT
, the ratio is held at one.
) × 64 taps when f
. The ratio is
1k
S_OUT
FAST MODE
/f
S_IN
counter to the
) × 2
10k
S_IN
ADAV801
S_OUT
20
/f
S_OUT
ratio for
100k
to f
S_IN
S_IN
>