ADAV801ASTZ Analog Devices Inc, ADAV801ASTZ Datasheet - Page 37

• Manufacturer Part Number: ADAV801ASTZ
• Description: IC CODEC AUDIO R-DVD 3.3V 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV801ASTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 102dB
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Adc/dac Resolution: 24b
• Interface Type: Serial (SPI)
• Mounting: Surface Mount
• Number Of Adc's: 2
• Number Of Dac's: 2
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 64
• Power Supply Type: Analog/Digital
• Sample Rate: 96KSPS
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV801EBZ - BOARD EVALUATION FOR ADAV801
• Lead Free Status / Rohs Status: Compliant

Transmitter Buffer Configuration—Address 0001101 (0x0D)
Table 39. Transmitter Buffer Configuration Register Bit Map
7
IU_Zeros3
Table 40. Transmitter Buffer Configuration Register Bit Descriptions
Bit Name
IU_Zeros[3:0]
TxBCONF3
TxBCONF[2:1]
TxBCONF0
Channel Status Switch Buffer and Transmitter—Address 0001110 (0x0E)
Table 41. Channel Status Switch Buffer and Transmitter Register Bit Map
7
Reserved
Table 42. Channel Status Switch Buffer and Transmitter Register Bit Description
Bit Name
Tx_A/B_Same
Disable_Tx_Copy
TxCSSWITCH
RxCSSWITCH
6
Reserved
6
IU_Zeros2
Description
Determines the number of zeros to be stuffed between IUs in a message up to a maximum of 8.
Transmitter user bits can be stored in separate buffers or stored together.
Configures the transmitter user bit buffer.
Determines the buffer size of the transmitter user bits when TxBCONF[2:1] is 01.
Description
Transmitter Channel Status A and B are the same. The transmitter reads only from the Channel Status A buffer and
places the data into the Channel Status B buffer.
Disables the copying of the channel status bits from the transmitter channel status buffer to the S/PDIF transmitter
buffer.
Toggle switch for the transmit channel status buffer.
Toggle switch for the receive channel status buffer.
0000 = 0.
0001 = 1.
…
0111 = 7.
1000 = 8.
0 = User bits are stored together.
1 = User bits are stored separately.
00 = Zeros are transmitted for the user bits.
01 = Transmitter user bit buffer size is configured according to TxBCONF0.
10 = User bits are written to the transmit buffer in IUs specified by the IEC60958-3 standard.
11 = Reserved.
0 = 384 bits with Preamble Z as the start of the buffer.
1 = 768 bits with Preamble Z as the start of the buffer.
0 = Channel status for A and B are separate.
1 = Channel status for A and B are the same.
0 = Copying transmitter channel status is enabled.
1 = Copying transmitter channel status is disabled.
0 = 24-byte Transmitter Channel Status A buffer can be accessed at address locations 0x38 through 0x4F.
1 = 24-byte Transmitter Channel Status B buffer can be accessed at address locations 0x38 through 0x4F.
0 = 24-byte Receiver Channel Status A buffer can be accessed at address locations 0x20 through 0x37.
1 = 24-byte Receiver Channel Status B buffer can be accessed at address locations 0x20 through 0x37.
5
Tx_A/B_Same
5
IU_Zeros1
4
Disable_Tx_Copy
4
IU_Zeros0
Rev. A | Page 37 of 60
3
TxBCONF3
3
Reserved
2
TxBCONF2
2
Reserved
1
TxBCONF1
1
TxCSSWITCH
0
TxBCONF0
0
RxCSSWITCH
ADAV801