DP8344BV National Semiconductor, DP8344BV Datasheet - Page 88

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

4 0 Remote Interface and Arbitration System (RIAS)
The BCP is now shown executing a local memory write with
remote data still pending in the latch At the end of this
instruction the BCP begins executing a series of internal
operations which do not require the bus RASM therefore
takes over and without waiting the Timing Control Unit exe-
cutes the Remote Write
4 2 6 Remote Rest Time
For the BCP to operate properly remote accesses to the
BCP must be separated by a minimal amount of time This
minimal amount of time has been termed ‘‘rest time’’
There are two causes for remote rest time The first cause is
implied in the functional state machine forms for remote ac-
cesses and can be explained as follows At the beginning of
every T-state the validity of a remote access is sampled for
that T-state To guarantee that the BCP recognizes the end
of a remote cycle the time between remote accesses must
be a minimum of one T-state plus set up and hold times
In the case of Latched Read and Fast Buffered Write the
validity of a remote access is not sampled on the first rising
edge of the CPU-CLK following XACK rising However on
all subsequent rising edges of the CPU-CLK the validity of
the remote access is sampled As a result if the remote
processor can terminate its remote access quickly after
XACK rises (within a T-state) up to a T-state may be added
to the above equation for Latched Read and Fast Buffered
Write modes (i e a second remote access should not begin
for two T-states plus set up and hold times after XACK rises
in Latched Read and Fast Buffered Write modes) On the
other hand if the remote processor does not terminate its
remote access within a T-state of XACK rising the above
equation (one T-state plus set up and hold times between
remote accesses) remains valid for Latched Read and Fast
Buffered Write modes
If these specifications are not adhered to the BCP may
sample the very end of one valid remote access and one
T-state later sample the very beginning of a second remote
access Thus the BCP will treat the second access as a
continuation of the first remote access and will not perform
the second read write The second access will be ignored
88
(Reference Figure 4-24 for the timing diagrams which dem-
onstrate how two remote accesses can be mistaken as
one )
The second source of remote rest time is due to the manner
in which the BCP samples the CMD signal CMD is sampled
once at the beginning of each remote access Due to the
manner in which CMD is sampled CMD will not be sampled
again if a second remote access begins within 1 5 T-states
plus a hold time after the BCP recognizes the end of the
first remote access If this happens the BCP will use the
value of CMD from the previous remote access during the
second remote access If the value of CMD is the same for
both accesses the second access will proceed as intended
However if the value of CMD is different for the two remote
accesses the second remote access will read write the
wrong location
The reader should note that the timing of the second source
of rest time begins at the same time that the BCP first sam-
ples the end of the previous remote access Thus when the
first source of rest time ends the second source of rest time
begins (Reference Figure 4-25 for timing diagrams for rest
time in all modes except Latched Write mode)
Latched Write Mode
Latched Write mode is a special case of rest time and
needs to be discussed separately from the other modes
The first cause of rest time affects every mode including
Latched Write In regards to the second source of rest time
Latched Write mode was designed to allow a second re-
mote access to start while a write is still pending (i e
WR-PEND
end of the previous write) the value of CMD is sampled for
the second remote access This allows Latched Write to
avoid the second cause of rest time discussed above
However if a remote access begins within one half a
T-state after WR-PEND rises CMD will not be sampled
again For this case if the value of CMD changes just after
WR-PEND rose and at the same time the remote access
begins the BCP will read write the wrong location (Refer-
ence Figure 4-26 for timing diagrams of rest time for latched
write mode )
e
0) Thus when WR-PEND rises (signaling the
(Continued)