DP8344BV National Semiconductor, DP8344BV Datasheet - Page 152

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

6 0 Reference Section
SBCA Subtract with Carry and
Syntax
SBCA Rs Rd
SBCA Rs mIr
Affected Flags
N Z C V
Description
Subtracts the active accumulator and the carry flag from the
source register Rs placing the result into the destination
specified The destination may be either a register Rd or
data memory via an index register mode
results are represented using the two’s complement format
Note that register bank selection determines which accumu-
lator is active
Example
Subtract the constant 109 from the index register IW (which
is 16 bits wide)
Instruction Format
SBCA Rs Rd
T-states
SBCA Rs Rd
SBCA Rs mIr
Bus Timing
SBCA Rs Rd
SBCA Rs mIr
Operation
SBCA Rs Rd
Rs
SBCA Rs mIr
Rs
SBCA Rs mIr
1
15
SUBA A A
SUB
SBCA R13 R13
b
b
1
accumulator
accumulator
Opcode
1
109 R12
Accumulator
0
1
b
b
1
carry bit
carry bit
9
Figure 6-1
Figure 6-7
2
3
Clear the accumulator
low byte of IW 109
high byte of IW borrow
register register
register indexed
Rd
Rd
data memory
(Continued)
4
mIr
Rs
TL F9336– 13
Negative
0
152
Figure 6-1
SHL Shift Left
Syntax
SHL Rsd b
Affected Flags
N Z C
Description
Shifts the contents of the register Rsd b bits to the left and
places the result back into that register Zeros are shifted in
from the right (i e from the LSB) The value b may specify
from 0 to 7 bit shifts The Carry flag contains the last bit
shifted out
Example
Place a new internal Address Stack Pointer into the Internal
Stack Pointer register ISP
Instruction Format
T-states
2
Bus Timing
Operation
ASP is located in register 20
1
15
MOVE ISP R8
AND
SHL
ORA
1
0
00001111B R8
R20 4
R20 ISP
Opcode
0
1
0
0
register
1
read ISP for DSP
save DSP only
left justify ASP
combine ASP
then place into ISP
R30 Assume that the new
7
(8-b)
4
a
Rsd
TL F 9336– 14
DSP
0