DP8344BV National Semiconductor, DP8344BV Datasheet - Page 82

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

4 0 Remote Interface and Arbitration System (RIAS)
state and A and AD continue to be tri-stated This allows the
Remote Processor to drive the Data Memory address and
data buses for the write Since DMEM is subject to wait
states RS
Memory wait states have been inserted
The last possible Memory Selection is Instruction Memory
pend on whether RASM is expecting the low byte or high
byte Instruction words are accessed low byte then high
byte and RASM powers up expecting the low Instruction
byte The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HIB)
If HIB is low the next state is RS
byte is written into the holding register ILAT If HIB is high
the high instruction byte is moved to I15–8 and ILAT is
moved to I7 –0 At the same time IWR is asserted low be-
ginning the write to instruction memory An IMEM access
like a DMEM access is subject to wait states and these
states will be looped on until all programmed instruction
memory wait states have been inserted
Note Resetting the BCP will reset HIB (i e HIB
After all of the programmed wait states are inserted into
RS
WAIT low a half T-state before the end of the last pro-
grammed wait state If there are no programmed wait states
WAIT must be asserted low a half T-state before the end of
RS
access is extended indefinitely All the RS
to state RS
wait state conditions are met and WAIT is high LCL remains
high in all RS
as well XACK returns high in this state indicating that the
data is written and the cycle can be terminated by the RP
This state begins the Termination Phase
MS1 –0
D
D
states more wait states may be added by asserting
to add wait states If WAIT remains low the remote
Memory Select bits in RIC (i e
will also force HIB to zero This way the instruction word boundary
can be reset without resetting the BCP
e
D4
E
01 The two possible next states for IMEM de-
is looped upon until all the programmed Data
E
on the next CPU-CLK after the programmed
states and A and AD remain in TRI-STATE
MS1–0
D5
and the low instruction
e
e
D
01 pointing to IMEM)
0) Writing 01 to the
states converge
82
On the next clock the state machine will enter RS
will return low The A and AD buses remain in TRI-STATE
for the first half T-state of RS
the Remote Processor is no longer using the buses and the
BCP CPU can make an access to Data Memory by asserting
LCL-BREQ If a local bus request is made a local bus grant
will be given to the Timing Control Unit If the preceding
access was a write of IMEM then HIB is switched and if the
access was to the high byte of IMEM then the PC is incre-
mented If RAE REM-WR is deasserted at this point the
next clock will bring RASM back to RS
until another remote access is initiated RS
RAE REM-WR is still true RASM will loop in RS
RAE REM-WR is no longer active at which time the state
machine will return to RS
In Figure 4-21 the BCP is executing the first of two Data
Memory writes when REM-WR goes low In response
XACK goes low waiting the Remote Processor At the end
of the first instruction although the BCP begins its second
write by taking ALE high RASM now takes control of the
bus and deasserts LCL high at the end of T
delay is built into this transfer to ensure that WRITE has
been deasserted high before the data bus is switched The
Timing Control Unit is now waited inserting remote access
wait states T
The remote access is permitted one T-state to settle on the
BCP address bus before WRITE goes low XACK then re-
turns high one T-state plus the programmed Data Memory
wait state T
time WRITE returns high at the same time and one T-state
later LCL returns low transferring bus control back to the
BCP The remote processor responds to XACK returning
high by deasserting REM-WR high although by this time the
BCP is well into its own memory write
Wd
Wr
later having satisfied the memory access
as RASM takes over
(Continued)
A
F
After the first half of RS
A
where it will loop
1
G
A one T-state
is entered if
F
and LCL
G
until
F