MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 61
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MC8641DVU1333JE
Manufacturer Part Number
MC8641DVU1333JE
Description
IC MPU DUAL CORE E600 1023FCCBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC8641DHX1000GE.pdf
(130 pages)
Specifications of MC8641DVU1333JE
Processor Type
MPC86xx PowerPC 32-Bit
Speed
1.333GHz
Voltage
1.05V
Mounting Type
Surface Mount
Package / Case
1023-FCCBGA
Family Name
MPC8xxx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
1.333GHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.05V
Operating Supply Voltage (max)
1.1V
Operating Supply Voltage (min)
1V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1023
Package Type
FCCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC8641DVU1333JE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(V
between 500 mV and –500 mV, in other words, V
phase. The peak differential voltage (V
is 1000 mV p-p.
13.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SDn_REF_CLK and
SDn_REF_CLK for PCI Express and Serial RapidIO.
The following sections describe the SerDes reference clock requirements and some application
information.
13.2.1
Figure 39
Freescale Semiconductor
OD
•
•
•
) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
The supply voltage requirements for XV
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to
SerDes Reference Clocks
shows a receiver reference diagram of the SerDes reference clocks.
shown in
50-Ω termination to SGND followed by on-chip AC-coupling.
Differential Mode and Single-ended Mode description below for further detailed requirements.
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND. For
example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven
by its current source from 0 mA to 16 mA (0–0.8 V), such that each phase of the differential
input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.
SGND DC, or it exceeds the maximum input current limitations, then it must be AC-coupled
off-chip.
SerDes Reference Clock Receiver Characteristics
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Figure
39. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
DIFFp
) is 500 mV. The peak-to-peak differential voltage (V
DD_
OD
SRDSn are specified in
is 500 mV in one phase and –500 mV in the other
Table 1
High-Speed Serial Interfaces (HSSI)
and
Table
2.
DIFFp-p
61
)