MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 18

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MC8641DVU1333JE

Manufacturer Part Number
MC8641DVU1333JE
Description
IC MPU DUAL CORE E600 1023FCCBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC8641DVU1333JE

Processor Type
MPC86xx PowerPC 32-Bit
Speed
1.333GHz
Voltage
1.05V
Mounting Type
Surface Mount
Package / Case
1023-FCCBGA
Family Name
MPC8xxx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
1.333GHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.05V
Operating Supply Voltage (max)
1.1V
Operating Supply Voltage (min)
1V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1023
Package Type
FCCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC8641DVU1333JE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Input Clocks
should meet the MPC8641 input cycle-to-cycle jitter requirement. Frequency modulation and spread are
separate concerns, and the MPC8641 is compatible with spread spectrum sources if the recommendations
listed in
It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is
operated at its maximum rated e600 core frequency should avoid violating the stated limits by using
down-spreading only.
SDn_REF_CLK and SDn_REF_CLK was designed to work with a spread spectrum clock (+0 to 0.5%
spreading at 30–33kHz rate is allowed), assuming both ends have same reference clock. For better results
use a source without significant unintended modulation.
4.2
The RTC input is sampled by the platform clock (MPX clock). The output of the sampling latch is then
used as an input to the counters of the PIC. There is no jitter specification. The minimum pulse width of
the RTC signal should be greater than 2x the period of the MPX clock. That is, minimum clock high time
is 2 × t
grounded if not needed.
4.3
Table 10
timing specifications for the MPC8641.
18
At recommended operating conditions. See
Parameter/Condition
EC n _GTX_CLK125 frequency
EC n _GTX_CLK125 cycle time
EC n _GTX_CLK125 peak-to-peak jitter
MPX
Table 9
provides the eTSEC gigabit reference clocks (EC1_GTX_CLK125 and EC2_GTX_CLK125) AC
Real Time Clock Timing
eTSEC Gigabit Reference Clock Timing
Frequency modulation
Frequency spread
Notes:
1. Guaranteed by design.
2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO
, and minimum clock low time is 2 × t
frequencies, must meet the minimum and maximum specifications given in
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
are observed.
Table 9. Spread Spectrum Clock Source Recommendations
Table 10. EC n _GTX_CLK125 AC Timing Specifications
Parameter
Table
2.
Symbol
t
f
t
G125J
G125
G125
MPX
. There is no minimum RTC frequency; RTC may be
Min
Min
125 ±100
Typical
ppm
8
Max
1.0
50
Table
Max
250
8.
Unit
kHz
%
Freescale Semiconductor
MHz
Unit
ns
ps
Notes
1, 2
1
Notes
3
1

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