MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 19

• Manufacturer Part Number: MC8641DVU1333JE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8641DVU1333JE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.333GHz
• Voltage: 1.05V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MPC8xxx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 1.333GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.05V
• Operating Supply Voltage (max): 1.1V
• Operating Supply Voltage (min): 1V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1023
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.4
The MPX platform clock frequency must be considered for proper operation of the high-speed PCI
Express and Serial RapidIO interfaces as described below.
For proper PCI Express operation, the MPX clock frequency must be greater than or equal to:
Note that at MPX = 400 MHz, cfg_plat_freq = 0 and at MPX > 400 MHz, cfg_plat_freq = 1. Therefore,
when operating PCI Express in x8 link width, the MPX platform frequency must be 400 MHz with
cfg_plat_freq = 0 or greater than or equal to 527 MHz with cfg_plat_freq = 1.
For proper Serial RapidIO operation, the MPX clock frequency must be greater than:
4.5
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,
see the specific section of this document.
Freescale Semiconductor
Parameter/Condition
EC n _GTX_CLK125 duty cycle
Notes:
1. Timing is guaranteed by design and characterization.
2. EC n _GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation.
3. ±100 ppm tolerance on EC n _GTX_CLK125 frequency
EC n _GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle
generated by the eTSEC GTX_CLK. See
for 10Base-T and 100Base-T reference clock.
Platform Frequency Requirements for PCI-Express and Serial
RapidIO
Other Input Clocks
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
The phase between the output clocks TSEC1_GTX_CLK and
TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase
between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK
(ports 3 and 4) is no more than 100 ps.
1000Base-T for RGMII, RTBI
Table 10. EC n _GTX_CLK125 AC Timing Specifications (continued)
2 × (0.80) × (Serial RapidIO interface frequency) × (Serial RapidIO link width)
GMII, TBI
527 MHz x (PCI-Express link width)
Section 8.2.6, “RGMII and RTBI AC Timing
16 / (1 + cfg_plat_freq)
t
G125H
Symbol
/t
NOTE
G125
64
Min
45
47
Typical
—
Specifications,” for duty cycle
Max
55
53
Unit
%
Notes
Input Clocks
1, 2
19