MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 23

• Manufacturer Part Number: MC8641DVU1333JE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8641DVU1333JE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.333GHz
• Voltage: 1.05V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MPC8xxx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 1.333GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.05V
• Operating Supply Voltage (max): 1.1V
• Operating Supply Voltage (min): 1V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1023
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.2
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
Table 18
Table 19
Table 20
Freescale Semiconductor
At recommended operating conditions
At recommended operating conditions.
At recommended operating conditions.
AC input low voltage
AC input high voltage
AC input low voltage
AC input high voltage
Controller Skew for
MDQS—MDQ/MECC
Note:
1. t
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
3. Maximum DDR1 frequency is 400 MHz.
bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget.
determined by the following equation: t
abs(t
CISKEW
provides the input AC timing specifications for the DDR2 SDRAM when Dn_
provides the input AC timing specifications for the DDR SDRAM when Dn_GV
provides the input AC timing specifications for the DDR SDRAM interface.
DDR SDRAM AC Electrical Characteristics
CISKEW
DDR SDRAM Input AC Timing Specifications
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Parameter
Parameter
Parameter
Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
) is the absolute value of t
Table 19. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
400, 533 MHz
400, 533 MHz
Table 20. DDR SDRAM Input AC Timing Specifications
600 MHz
600 MHz
600 MHz
533 MHz
400 MHz
Symbol
Symbol
Symbol
CISKEW
t
DISKEW
CISKEW
V
V
V
V
—
—
—
IH
IH
IL
IL
.
=+/–(T/4 – abs(t
D n _MV
D n _MV
D n _MV
–240
–300
–365
Min
Min
Min
REF
REF
REF
—
—
—
CISKEW
+ 0.25
+ 0.20
+ 0.31
)) where T is the clock period and
D n _MV
D n _MV
D n _MV
Max
Max
Max
240
300
365
REF
REF
REF
—
—
– 0.25
– 0.20
– 0.31
DISKEW
Unit
Unit
Unit
DDR and DDR2 SDRAM
ps
—
—
—
V
V
V
V
GV
DD
.This can be
DD
(typ)=2.5 V.
(typ)=
Notes
Notes
Notes
1, 2
—
—
—
—
—
3
3
1.8 V.
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