MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 44

• Manufacturer Part Number: MC8641DVU1333JE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8641DVU1333JE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.333GHz
• Voltage: 1.05V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MPC8xxx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 1.333GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.05V
• Operating Supply Voltage (max): 1.1V
• Operating Supply Voltage (min): 1V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1023
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Ethernet Management Interface Electrical Characteristics
Figure 23
Figure 24
44
At recommended operating conditions with OV
MDIO to MDC hold time
MDC rise time
MDC fall time
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency
3. This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency
4. Guaranteed by design.
5. t
(reference)(state)
symbolizes management data timing (MD) for the time t
invalid (X) or data hold time. Also, t
signals (D) reach the valid state (V) relative to the t
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
divided by 64.)
is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz
and the minimum frequency is 1.7 MHz.)
MPXCLK
Parameter/Condition
provides the AC test load for eTSEC.
shows the MII management AC timing diagram.
is the platform (MPX) clock
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Output will see a 50-Ω load since what it sees is the transmission line.
for inputs and t
(Output)
(Input)
MDIO
MDIO
MDC
Table 39. MII Management AC Timing Specifications (continued)
Output
Figure 24. MII Management Interface Timing Diagram
(first two letters of functional block)(reference)(state)(signal)(state)
t
MDDVKH
MDCH
DD
Symbol
t
MDDXKH
t
t
t
MDDVKH
is 3.3 V ± 5%.
MDCR
MDHF
Figure 23. eTSEC AC Test Load
t
MDC
symbolizes management data timing (MD) with respect to the time data input
Z
t
MDKHDX
0
1
= 50 Ω
MDC
NOTE
MDC
clock reference (K) going to the high (H) state or setup time. For
Min
—
—
0
from clock reference (K) high (H) until data outputs (D) are
t
MDCF
t
MDDXKH
(first two letters of functional block)(signal)(state)
R
Typ
—
—
—
t
L
MDCR
= 50 Ω
for outputs. For example, t
OV
Max
10
10
—
DD
/2
Freescale Semiconductor
Unit
ns
ns
ns
MDKHDX
Notes
—
4
4