MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 48

• Manufacturer Part Number: MC8641DVU1333JE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8641DVU1333JE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.333GHz
• Voltage: 1.05V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MPC8xxx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 1.333GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.05V
• Operating Supply Voltage (max): 1.1V
• Operating Supply Voltage (min): 1V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1023
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Local Bus
48
LGTA/LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output transition (LATCH
hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except LAD/LDP
and LALE)
Local bus clock to output high impedance for LAD/LDP
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal
5. Input timings are measured at the pin.
6. The value of t
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
8. Guaranteed by characterization.
for inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
for clock one(1). Also, t
to the output (O) going invalid (X) or output hold time.
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK
by t
complementary signals at BV
in question for 3.3-V signaling levels.
through the component pin is less than or equal to the leakage current specification.
LBKHKT
.
LBOTOT
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
(First two letters of functional block)(reference)(state)(signal)(state)
Table 42. Local Bus Timing Parameters—PLL Bypassed (continued)
is the measurement of the minimum time between the negation of LALE and any change in LAD
Parameter
LBKHOX
DD
symbolizes local bus timing (LB) for the t
/2.
Symbol
t
t
t
t
t
t
t
t
t
t
LBKLOV1
LBKLOV2
LBKLOV3
LBKLOV4
LBKLOX1
LBKLOX2
LBKLOZ1
LBKLOZ2
LBIXKL2
LBOTOT
for outputs. For example, t
(First two letters of functional block)(signal)(state) (reference)(state)
1
LBK
LBK
clock reference (K) to go high (H), with respect
clock reference (K) goes high (H), in this case
–1.3
–3.2
–3.2
Min
1.5
—
—
—
—
—
—
Max
–0.3
–0.1
0.2
0.2
—
—
—
—
0
0
LBIXKH1
Freescale Semiconductor
symbolizes local bus
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4, 5
6
4
4
4
4
4
7
7