MC8641DVU1333JE Freescale Semiconductor, MC8641DVU1333JE Datasheet - Page 17

• Manufacturer Part Number: MC8641DVU1333JE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8641DVU1333JE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.333GHz
• Voltage: 1.05V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MPC8xxx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 1.333GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.05V
• Operating Supply Voltage (max): 1.1V
• Operating Supply Voltage (min): 1V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1023
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4
Table 7
4.1
Table 8
At recommended operating conditions (see
4.1.1
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference
emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise
magnitude in order to meet industry and government requirements. These clock sources intentionally add
long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in
considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter
Freescale Semiconductor
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the
2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the short term jitter only and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
resulting SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective
maximum or minimum operating frequencies. See
“e600 to MPX clock PLL Ratio,”
allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the
frequency modulation for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee
what is supported based on design.
Input Clocks
provides the system clock (SYSCLK) DC specifications for the MPC8641.
provides the system clock (SYSCLK) AC timing specifications for the MPC8641.
High-level input voltage
Low-level input voltage
Input current
(V
Note:
1. Note that the symbol V
System Clock Timing
IN
SYSCLK and Spread Spectrum Sources
1
Parameter/Condition
= 0 V or V
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Table 7. SYSCLK DC Electrical Characteristics (OVDD = 3.3 V ± 165 mV)
Parameter
IN
= V
DD)
IN
, in this case, represents the OV
Table 8. SYSCLK AC Timing Specifications
Table
for ratio settings.
2) with OV
Symbol
t
KHK
V
V
I
IN
Symbol
IH
f
t
IL
t
SYSCLK
SYSCLK
KH
DD
/t
—
SYSCLK
, t
Section 18.2, “MPX to SYSCLK PLL Ratio,”
= 3.3 V ± 165 mV
KL
IN
–0.3
Min
Min
0.6
66
40
—
—
symbol referenced in
2
6
.
Typical
1.0
—
—
—
—
OV
DD
Max
0.8
±5
+ 0.3
166.66
Table 1
Max
150
1.2
60
—
and
and
MHz
Unit
Table
ns
ns
ps
%
Section 18.3,
Unit
μA
V
V
2.
Table 8
Notes
Input Clocks
4, 5
—
1
2
3
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