MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 584

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Abort Task Routine, 9-86
Absolute Long Address Mode, 2-20
Absolute Short Address Mode, 2-20
Access Time Calculations, Memory, 12-14-12-17
Accesses, Read-Modify-Write, 6-10
Acknowledge, Breakpoint, 8-10
Activity,
Actual Instruction Cache Case, 11-11
Adapter Board,
Address Bus, 5-4, 7-4, 7-30ff, 12-4
Address Encoding, CPU Space, 7-68
Address Error Exception, 8-9, 10-72
Address Offset Encoding, 7-9
Address Register
Address Registers, 1-6, 2-3
Address Strobe Signal, 5-5, 7-3, 7-4, 7-26ff
Address Translation, 9-13
Addressing,
T i m i n g Table, 11-40
Address Space Types, 4-3
Aids, Debugging, 12-35
Arbitration, Bus, 7-96
Arithmetic/Logical Instruction,
AS Signal, 5-5, 7-3, 7-4, 7-26ff
MOTOROLA
Data Bus, 12-11
Processor,
MC68020, 12-1
Signal Routing, 12-1
Direct Mode, 2-10
Indirect Displacement Mode, 2-12
Indirect Index (Base Displacement) Mode, 2-13
Indirect Index (8-Bit Displacement) Mode, 2-12
Indirect Mode, 2-10
Indirect Postincrement Mode, 2-10
Indirect Predecrement Mode, 2-11
Cache, 7-3, 9-4, 9-17
Cache Entry, 9-18
General Flowchart, 9-14
Capabilities, 2-25
Compatibility, M68000, 2-36
Indexed, 2-26
Indirect, 2-28
Indirect Absolute Memory, 2-28
Structure, 2-36
Mode Summary, 2-31
Modes, 1-10, 2-8
Immediate, Timing Table, 11-42
Even Alignment, 11-9
Odd Alignment, 11-10
A
MC68030 USER'S MANUAL
INDEX
Assignment, Pin, 14-2, 14-3
Assignments, Exception Vector, 8-2
Asynchronous
ATC, 7-3, 9-4, 9-17
Autovector Interrupt Acknowledge Cycle, 7-71
Autovector Signal, 5-8, 7-6, 7-29, 7-71ff, 8-20
AVEC Signal, 5-8, 7-6, 7-29, 7-71ff, 8-20
Average No Cache Case, 11-8
A0-A1 Signals, 7-8, 7-9, 7-22ff
A0-A31 Signals, 5-4, 7-4, 7-31ff
A0-A7, 1-6
BERR Signal, 5-9, 6-11, 7-6, 7-27ff, 8-7, 8-22, 8-26,
Best Case, 11-7
BG Signal, 5-9, 7-43, 7-96ff
BGACK Signal, 5-9, 7-97ff
Binary-Coded Decimal Instruction Timing Table,
Binary-Coded Decimal Instructions, 3-10
Bit,
Bus Operation, 7-27
Byte
Cycle Signal Assertion Results, 7-78, 7-79
Long-Word Read Cycle Flowchart, 7-32
Read Cycle, 7-31
Sample Window, 7-3
Word
Write Cycle, 7-37
Timing, 7-72
Read-Modify:Write Cycle, 7-45
Entry, 9-17
CA, 10-35
CD, 6-21
CED, 6-21
CEI, 6-22
CI, 6-22
Clear Data Cache, 6-21
11-43
Write Cycle, 32-Bit Port, Timing, 7-38
Read Cycle, 32-Bit Port, Timing, 7-33
Read Cycle Flowchart, 7-32
Read-Modify-Write Cycle, 32-Bit Port, Timing,
32-Bit Port, Timing, 7-33
Write Cycle, 32-Bit Port, Timing, 7-39
32-Bit Port, Timing, 7-38
Flowchart, 7-44
Read Cycle, 32-Bit Port, Timing, 7-33
Flowchart, 7-37
Creation Flowchart, 9-42
7-45
B
INDEX-1
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