MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 481

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

11
11.5 EFFECT OF W A I T S T A T E S
11-18
The effect of wait states on data accesses may be accounted for in the
To add the effect of wait states on data accesses:
The following computations use the general Equation (1 1-2):
The constraints of a system design may require the insertion of wait states
in memory cycles. When the bus or the memory device requires many wait
states, instruction execution time is increased. However, one or two wait
states may have little effect on instruction timing. Often the only effect of
one or more wait states is to reduce bus idle time.
instruction-cache-case
Execution Time
lb.
la.
lc.
operand read, add the number of wait states (in clocks) to the tail
and instruction-cache-case (CC) times. The head is not affected.
add the number of wait states to the CC time only. The head and
tail are not affected.
two data reads (for the address fetch), add the number of wait states
for two reads to the CC time. Add the number of wait states for one
For nonmemory indirect effective address timings that include an
For memory indirect effective address timings that use the calculate
< e a > tables and have only one data read (for the address fetch),
For memory indirect effective address timings (fetch < e a > ) that have
data read to the tail. The head is not affected.
= 3 + 2 + 1 0 + 3 + 1 + 4 + 2 + 1 2
= 37 clock periods
= CCea 1 + [CCop 1 - min(HoPl,Tea 1 )] + [CCea 2 - min(Hea2,TOPl )] +
= 3 + [2- min(0,1)] + [10- min(4,0)] + [3 - min(0,0)] + [2- min(1,1)] +
[4- min(2,0)] + [2- min(0,0)] + [12- min(0,0)]
[CCoP2- min(HoP2,Tea2) ] + [CCea 3 - min(Hea3,ToP2)] +
[CCoP3 - min(HoP3,Tea3) ] + [CCea 4 - min(Hea4,ToP3)] +
[CCoP4- min(H o P4,Tea4) ]
timings.
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