MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 219

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7
7-58
State 4
State 5
State 6
State 3
Idle States
from the appropriate byte(s) of the data bus (D24-D31, D16-D23, D8-D15,
the preceding read portion of the cycle; the data bus is not driven until $6.
tention. It must also negate STERM within two clocks after asserting STERM;
The processor does not assert any new control signals during the idle
The processor asserts ECS and OCS in $4 to indicate that an external cycle
The selected device uses R/W, CLK, SIZ0-SIZ1, and A0-A1 to latch data
The processor negates AS, DS, and DBEN during $3. If more than one read
cycle is required to
When finished with the read cycle, the processor holds the address, R/W,
The external device must keep its data asserted throughout the synchron-
ous hold time for data from the beginning of $3. The device must remove
the
otherwise, the processor may inadvertently use STERIVI for the next bus
cycle.
states, but it may begin the modify portion of the cycle at this time. The
is beginning. The processor drives R/W low for a write cycle. CLOUT also
becomes valid, indicating the state of the MMU CI bit in the address trans-
operation to be performed, the address lines may change during $4.
address bus is valid. The processor also asserts DBEN during $5, which
can be used to enable external data buffers.
asserts STERM when it has successfully stored the data. If the device does
states are inserted. Note that for zero-wait-state synchronous write cycles,
and FCO-FC2 valid in preparation for the write portion of the= cycle.
R/W signal remains in the read mode until $4 to prevent bus conflicts with
lation descriptor or in the appropriate TTx register. Depending on the write
In state 5 ($5), the processor asserts AS to indicate that the address on the
During $6, the processor places the data to be written onto the D0-D31,
and D0-D7). SIZ0-SIZ1 and A0-A1 select the data bus sections. The device
not assert STERM by the rising edge of $6, the processor inserts wait states
until it is recognized. The processor asserts DS at the end o f $6 if wait
DS is not asserted.
data
within
one-clock
read
MC68030 USER'S MANUAL
in the operand(s), S0-$3 are repeated accordingly.
cycle
after
asserting STERM to avoid bus
MOTOROLA
con-